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    Single-drive level shifter, with low dynamic impedance
    1.
    发明公开
    Single-drive level shifter, with low dynamic impedance 失效
    Pegelumsetzer mit Einzelsteuerung und niedriger dynamischer Impedanz。

    公开(公告)号：EP0468209A2

    公开(公告)日：1992-01-29

    申请号：EP91110382.8

    申请日：1991-06-24

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Martignoni, Fabrizio ,  Diazzi, Claudio ,  Pidutti, Albino ,  Vio, Fabio

    IPC: H03K17/06 ,  H03K17/04

    CPC classification number: H03K17/06 ,  H03K17/04123 ,  H03K17/063

    Abstract: A level shifter, particularly suited for driving power stages for supplying power to integrated circuits, includes a DMOS transistor (40) which is driven by a time-controlled signal and has a load resistor (44), as its drain load. A shifted output signal developes at the ends of said load resistor. The drain (V1) of the DMOS transistor is connected to the input of an inverter (46), while a Zener diode (54) and a second transistor (52) are connected in parallel to the load resistor (44), the gate of the second transistor (52) being driven by the output of the inverter (46). The output of the inverter (46) can be connected to the input of a drive stage (48), the output of which drives a power stage (50) for supplying power to an integrated circuit.

    Abstract translation: 特别适用于驱动向集成电路供电的功率级的电平移位器包括由时间控制信号驱动并具有负载电阻（44）作为其漏极负载的DMOS晶体管（40）。 移位的输出信号在所述负载电阻的两端形成。 DMOS晶体管的漏极（V1）连接到反相器（46）的输入端，而齐纳二极管（54）和第二晶体管（52）并联连接到负载电阻（44），栅极 所述第二晶体管（52）由所述逆变器（46）的输出驱动。 逆变器（46）的输出可以连接到驱动级（48）的输入，驱动级（48）的输出驱动用于向集成电路供电的功率级（50）。

    Protection of power converters from voltage spikes
    3.
    发明公开
    Protection of power converters from voltage spikes 失效
    电压转换器的保护

    公开(公告)号：EP0371928A3

    公开(公告)日：1990-09-26

    申请号：EP89830494.4

    申请日：1989-11-13

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Cuomo, Andrea ,  Diazzi, Claudio ,  Rischmuller, Klaus

    IPC: H02M3/158

    CPC classification number: H03K17/08142 ,  H02M3/1582

    Abstract: In a power converter circuit directly or indirectly con­nected to the power distribution network, the protection from voltage spikes which may occur on the power supply rail is implemented in a manner as to consent the utilization of at least a portion of the energy associated with the spike by storing portion of said energy in the reactive components of the converter circuit itself instead of dissipating completely the energy through a dissipating element as in prior art arrangements. The novel circuit arrangement utilizes one or two spike sensors the output signal or signals of which are fed to logic gates which determine a certain configuration of the analog switches of the converter circuit. A protection voltage limiting element (zener diode, avalanche diode, voltage-dependent resistor, etc.) is functionally connected across the analog switch connected between the reactive element of the converter circuit and the power supply rail and limits to its intrinsic breakdown voltage the maximum voltage across the switch.

    Current limiter for constant current for switching driving devices
    4.
    发明公开
    Current limiter for constant current for switching driving devices 失效
    StrombegrenzerfürKonstantstromfüreinen Treiber einesSchaltgerätes。

    公开(公告)号：EP0242759A2

    公开(公告)日：1987-10-28

    申请号：EP87105439.1

    申请日：1987-04-13

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Cini, Carlo ,  Diazzi, Claudio ,  Gattavari, Giuseppe

    IPC: H01H47/32 ,  H03K17/08

    CPC classification number: H01H47/325 ,  H02H3/087

    Abstract: The switching driving device with current limitation, operating reliably even with high switching frequencies, comprises a drive stage (10) receiving at the input a timing clock signal (MCl) at a preset frequency and generating at the output a drive signal synchronized with the timing clock signal, a power element (11) connected at the input to the drive stage, receiving therefrom the drive signal and generating a load supply signal, a load (14) fed by the power element, and a current sensor (16,17) generating an overload signal when the current in the load has reached a preset threshold. The current limitation is obtained through a memory element (21) connected to the current sensor (16,17) and disabling the drive stage (10) in the presence of the overload signal. In order to obtain a reliable operation, in the presence of the overload signal the drive stage is controlled at a switching frequency which is lower than the preset frequency of the timing clock signal.

    Abstract translation: 具有电流限制的开关驱动装置即使具有高开关频率也可靠地工作，包括驱动级（10），其在输入端接收预定频率的定时时钟信号（MCl），并在输出端产生与定时同步的驱动信号 时钟信号，连接到驱动级的输入端的功率元件（11），从其接收驱动信号并产生负载电源信号，由功率元件供电的负载（14）和电流传感器（16,17） 当负载中的电流达到预设阈值时产生过载信号。 通过连接到电流传感器（16,17）的存储元件（21）并且在存在过载信号的情况下禁用驱动级（10）来获得电流限制。 为了获得可靠的操作，在存在过载信号的情况下，驱动级被控制在低于定时时钟信号的预置频率的开关频率。

    An integrated control circuit with a level shifter for switching an electronic switch
    6.
    发明公开
    An integrated control circuit with a level shifter for switching an electronic switch 失效
    与控制滑阀集成控制电路，用于切换的电子开关

    公开(公告)号：EP0703667A1

    公开(公告)日：1996-03-27

    申请号：EP94830436.5

    申请日：1994-09-16

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Diazzi, Claudio ,  Martignoni, Fabrizio ,  Tarantola, Mario

    IPC: H03K17/687

    CPC classification number: H03K17/687 ,  H03K17/161

    Abstract: A circuit for controlling a power transistor connected between two supply terminals (ground, V H ) is described, in series with a load (L) and comprising a control logic circuit (LG) which produces a signal at two levels with respect to a reference terminal (ground), a level shifter (LS1) connected between the control circuit (LG) and the power transistor (T1), and which produces a signal at two levels referred to the node (S1) between the power transistor (T1) and the load (L). The level shifter (LS1) includes a flip-flop (RS) the output of which controls the power transistor (T1) as well as two transistors (M10, M9) driven by the control logic circuit (LG) to switch alternatively and provide switchin signals on the "set" and "reset" inputs (S,R) of the flip-flop (RS) via two resistors (R4, R3). Two parasitic current generators (Tp1, Tp2) inject current into the two resistors (R4, R3) during the phase in which the power transistor (T1) is cut off. To prevent this current from causing unwanted switching of the flip-flop a resistor (R4) connected to the "set" terminal (S) of the flip-flop has a lower resistance than that of the other resistor (R3).

    Abstract translation: 一种用于控制连接的两个电源端子（接地，VH）之间的功率晶体管电路进行了说明，在串联的负载（L），并且包括一个控制逻辑电路（LG）其中在两个层面相对于产生一个信号到参考端子 （接地），电平移位器（LS1），连接在控制电路（LG）和功率晶体管（T1）之间，并且其产生在由称为功率晶体管（T1）和之间的节点（S1）两个级别的信号 负载（L）。 电平移位器（LS1）包括触发器（RS），其中控制由所述控制逻辑电路（LG）驱动的功率晶体管（T1）以及两个晶体管（M10，M9），以交替地切换并提供switchin输出 信号经由两个电阻（R4，R3）触发器的“置位”和“复位”输入端（S，R）（RS）。 两个寄生电流发生器（TP1，TP2）电流注入期间，其中功率晶体管（T1）关断，相位的两个电阻器（R4，R3）。为了防止这种电流引起的不期望的切换触发器的电阻器 （R4）连接到所述触发器的“置位”端（S）具有比其它电阻器（R3）的更低的电阻。

    Integrated device with a surface electrical field delimiting structure and relative fabrication process
    7.
    发明公开
    Integrated device with a surface electrical field delimiting structure and relative fabrication process 失效
    与用于表面电场和制造工艺的结构定义的集成装置

    公开(公告)号：EP0689248A1

    公开(公告)日：1995-12-27

    申请号：EP94830300.3

    申请日：1994-06-20

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Diazzi, Claudio ,  Murari, Bruno ,  Mastromatteo, Ubaldo ,  Contiero, Claudio

    IPC: H01L23/58

    CPC classification number: H01L23/585 ,  H01L23/315 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The resin sealing layer (30) enclosing the device (10) is biased to a low voltage by means of an anchoring structure (32) formed close to high-voltage contact pads (23). The anchoring structure is formed by a metal region (24) deposited on the surface of the device (10) and contacting the resin layer (30), and by a deep region (28) extending from the surface (19) of the device, beneath the metal region (24), to the substrate (11). The electrical field in the resin layer (30) is confined between the high-voltage pads (23) and the anchoring structure (32) and prevented from generating polarity inversions in the semiconductor material at the low-voltage contact pads (25) or any other points at which the resin layer (30) contacts the body of semiconductor material (11, 12).

    Abstract translation: 包围装置（10）的树脂密封层（30）由形成为接近高电压接触垫（23）的锚定结构（32）的装置被偏置到低电压。 锚定结构被淀积在器件（10）和接触的树脂层（30）的表面上的金属区（24）形成，并且通过深区域（28）从所述装置的表面（19）延伸， 下的金属区（24）与基板（11）。 在树脂层中的电场（30）的高电压焊盘（23）和所述锚定结构（32）之间密闭，并从在低压接触垫（25）或任何在半导体材料中产生的极性反转防治 其他点，其中所述树脂层（30）接触所述主体的半导体材料（11，12）。

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