公开(公告)号：JP3554350B2

公开(公告)日：2004-08-18

申请号：JP31768893

申请日：1993-12-17

Applicant: エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： クレイグ ディクソン デイ． ,  ジェイ． ハント マイケル

IPC: H01L25/00 ,  H01L23/495 ,  H01L23/58 ,  H01M2/10 ,  H01M2/20

CPC classification number: H01L23/58 ,  H01L23/49593 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01M2/1044 ,  H01M2/20 ,  Y10S257/924 ,  Y10T29/49121 ,  Y10T29/49171 ,  H01L2224/45099 ,  H01L2924/00

公开(公告)号：JP2003332946A

公开(公告)日：2003-11-21

申请号：JP2003139113

申请日：2003-05-16

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： DARBEL NICOLAS ,  BELVEZE FABRICE ,  FAUX GREGORY

IPC: H04B1/707

CPC classification number: H04B1/70735 ,  H04B1/7083 ,  H04B1/709

Abstract: PROBLEM TO BE SOLVED: To provide an improved technique for initially acquiring a synchronous code group and frame alignment data, using a UMTS-FDD receiver. SOLUTION: For completing a step 2 process, a different synchronous channel is used. In more detail, a complete synchronous channel correlator is used for a demodulation such that it correlates received signals in known time slots for coupling a primary synchronous code with a plurality of secondary synchronous codes each. The coupled correlation provides a step 2 performance improved in the view of the acquisition time and the signal to noise ratio. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：使用UMTS-FDD接收机提供用于初始获取同步码组和帧对准数据的改进技术。

解决方案：为了完成步骤2的处理，使用不同的同步通道。 更详细地，使用完整的同步信道相关器进行解调，使得它将已知时隙中的接收信号相关联，以将主同步码与多个次同步码各自耦合。 耦合相关提供了在采集时间和信噪比方面改进的步骤2性能。 版权所有（C）2004，JPO

公开(公告)号：JP2003076499A

公开(公告)日：2003-03-14

申请号：JP2002231742

申请日：2002-08-08

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： LIN WEN

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F13/18 ,  G11B5/55

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0674 ,  G11B5/5547

Abstract: PROBLEM TO BE SOLVED: To provide a technique for improving command queue rearranging process with the load of processor resource decreased.
SOLUTION: This invention provides a hardware command queue with a memory device for a mass memory system. Plural entries are demarcated within the memory device, at least several among which are active entries. Among the active entries, at lease several are associated with pending access commands with at least one entry as a head entry associated with the active command in operation. Physical target position is stored in each active entry with the calculated servo distance stored in each active entry. A link list including a pointer for defining execution sequence is stored together with the command queue.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于改善处理器资源负载的命令队列重排过程的改进技术。 解决方案：本发明提供了一种具有用于大容量存储器系统的存储器装置的硬件命令队列。 多个条目在存储设备内被划分，其中至少几个是活动条目。 在活动条目中，至少有几个与等待访问命令相关联，其中至少有一个条目作为与正在运行的活动命令相关联的头条目。 物理目标位置存储在每个活动条目中，计算出的伺服距离存储在每个活动条目中。 包括用于定义执行顺序的指针的链接列表与命令队列一起存储。

公开(公告)号：JP2003068028A

公开(公告)日：2003-03-07

申请号：JP2002186708

申请日：2002-06-26

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： OZDEMIR HAKAN

IPC: G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  G11B21/10 ,  H03M7/16 ,  H03M13/41

CPC classification number: H03M7/16 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10175 ,  G11B20/10222 ,  G11B20/10296 ,  G11B20/1403 ,  G11B20/18 ,  G11B2020/1282 ,  G11B2020/1284 ,  G11B2020/1484 ,  G11B2020/1859 ,  G11B2020/1863 ,  H03M13/41 ,  H03M13/6343

Abstract: PROBLEM TO BE SOLVED: To provide a circuit and a method to detect a phase of a servo signal so as to allow a servo circuit to compensate for a reversed-connected head. SOLUTION: A detector recovers servo data from a servo signal generated by a read/write head and determines a head-connection polarity from the recovered servo data. Such a detector allows the servo circuit to compensate for a reversed-connected read/write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Abstract translation: 要解决的问题：提供一种检测伺服信号的相位的电路和方法，以便允许伺服电路补偿反向连接的磁头。 解决方案：检测器从读/写头产生的伺服信号中恢复伺服数据，并根据恢复的伺服数据确定磁头连接极性。 这种检测器允许伺服电路补偿反连接的读/写头，因此允许制造商放弃耗时和昂贵的测试来确定磁头是否正确地连接到伺服电路。

公开(公告)号：JP2003022624A

公开(公告)日：2003-01-24

申请号：JP2002187536

申请日：2002-06-27

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： OZDEMIR HAKAN

IPC: G11B5/09 ,  G11B5/596 ,  G11B20/12 ,  G11B21/10

CPC classification number: G11B5/59633

Abstract: PROBLEM TO BE SOLVED: To provide an improved data storage medium, particularly a data- storage disk having a few or no spin-up wedges.
SOLUTION: This data-storage disk has a disk sector for storing data and a servo wedge located at the beginning of the sector. The servo wedge identifies the sector in conjunction with both an initial positioning of a read-write head and a data read and write operation. By using a servo wedge to provide both an initial head position on disk spin up and a head position during a read or write operation, one can increase a disk's data-storage capacity by reducing the number of, or altogether eliminating, spin-up wedges.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供改进的数据存储介质，特别是具有少量或不具有旋转楔形的数据存储盘。 解决方案：该数据存储盘具有用于存储数据的磁盘扇区和位于扇区开头的伺服楔。 伺服楔同时结合读写头的初始定位和数据读写操作来识别扇区。 通过使用伺服楔以在读或写操作期间提供磁盘上升的初始头部位置和头部位置，可以通过减少旋转楔子的数量或完全消除磁盘的数据存储容量来增加磁盘的数据存储容量 。

公开(公告)号：JP2002366444A

公开(公告)日：2002-12-20

申请号：JP2002128327

申请日：2002-04-30

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： LAURENT DUANE GILES

IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00

CPC classification number: G06F11/1044

Abstract: PROBLEM TO BE SOLVED: To provide a technology for reducing a soft error in a dynamic memory device.
SOLUTION: This memory device is provided with a dual port memory equipped with a first port corresponding to an externally started memory access operation and a second port for dealing with the memory access operation related with an error check and error correcting operation. An error module connected to the second port of the dual port memory performs an error check operation with respect to a word read from the dual port memory. An error controller connected to the error module controls the error module to perform the error check operation with respect to each word successively read from the dual port memory through the second port. The error check operation is performed substantially in parallel with the externally started memory access operation to be performed by using the first port of the dual port memory.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供用于减少动态存储装置中的软错误的技术。 解决方案：该存储装置配备有配备有对应于外部启动的存储器访问操作的第一端口的双端口存储器和用于处理与错误校验和纠错操作相关的存储器访问操作的第二端口。 连接到双端口存储器的第二端口的错误模块相对于从双端口存储器读取的字执行错误检查操作。 连接到错误模块的错误控制器控制错误模块，对通过第二端口从双端口存储器连续读取的每个字执行错误检查操作。 基本上与通过使用双端口存储器的第一端口执行的外部启动的存储器访问操作并行执行错误检查操作。

公开(公告)号：JP6462203B2

公开(公告)日：2019-01-30

申请号：JP2013164297

申请日：2013-08-07

Applicant: エスティーマイクロエレクトロニクス,インコーポレイテッド ,  STMicroelectronics,Inc

Inventor： チイン リィウ ,  プラサンナ カーレ ,  ニコラス ルベ

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/336

公开(公告)号：JP6336255B2

公开(公告)日：2018-06-06

申请号：JP2013164180

申请日：2013-08-07

Applicant: エスティーマイクロエレクトロニクス,インコーポレイテッド ,  STMicroelectronics,Inc

Inventor： チイン リィウ ,  ニコラス ルベ ,  プラサンナ カーレ

IPC: H01L21/76 ,  H01L27/12 ,  H01L21/336 ,  H01L29/786 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76264

公开(公告)号：JP6249666B2

公开(公告)日：2017-12-20

申请号：JP2013164024

申请日：2013-08-07

Applicant: エスティーマイクロエレクトロニクス,インコーポレイテッド ,  STMicroelectronics,Inc

Inventor： チイン リィウ ,  プラサンナ カーレ ,  ニコラス ルベ

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L21/768 ,  H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/76816 ,  H01L21/823425 ,  H01L21/823864 ,  H01L29/41766 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

公开(公告)号：JP2014110430A

公开(公告)日：2014-06-12

申请号：JP2013247490

申请日：2013-11-29

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc.

Inventor： NICOLAS LOUBET ,  PRASANNA KHARE

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/41 ,  H01L29/417

CPC classification number: H01L27/088 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To prevent leakage of charge between a semiconducting channel and a substrate in a strained silicon FinFET device.SOLUTION: By inserting an insulating layer between the channel (fin) and the substrate, the fin is isolated from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins is grown epitaxially from the silicon substrate, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.

Abstract translation: 要解决的问题：为了防止应变硅FinFET器件中的半导体沟道和衬底之间的电荷泄漏。解决方案：通过在沟道（鳍片）和衬底之间插入绝缘层，翅片与物理物质隔离 并电。 为了形成隔离的FinFET器件，从硅衬底外延生长双层鳍片的阵列，在相邻鳍片之间提供局部绝缘的氮化物柱之间。 然后，可以在离开上部翅片层的同时去除下部翅片层，从而产生悬挂在硅表面上方的氮化物柱和半导体翅片的交错排列。 然后可以用氧化物填充在上鳍片下方的所得间隙，以将翅片通道阵列与基底隔离。