公开(公告)号：US20190042308A1

公开(公告)日：2019-02-07

申请号：US16118840

申请日：2018-08-31

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Krishna Bhuyan

IPC: G06F9/48

Abstract: Technologies for providing efficient scheduling of functions include a compute device. The compute device is configured to obtain a function dependency graph indicative of data dependencies between functions to be executed in a networked set of compute devices, perform a cluster analysis of the execution of the functions in the networked set of compute devices to identify additional data dependencies between the functions, and update, based on the cluster analysis, the function dependency graph.

公开(公告)号：US20190042277A1

公开(公告)日：2019-02-07

申请号：US15856644

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: G06F9/4401 ,  G06F9/445

Abstract: Technologies for utilizing a runtime code present in an option read only memory (ROM) include a sled that includes a device having an option ROM with runtime code indicative of a runtime function of the device. The sled is to detect, in a boot process, the device on the sled, access, in the boot process, the runtime code in the option ROM of the detected device to identify the runtime function, and execute, in a runtime process, the runtime function associated with the runtime code. Other embodiments are also described and claimed.

公开(公告)号：US20190042136A1

公开(公告)日：2019-02-07

申请号：US15856556

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: G06F3/06

Abstract: Technologies for dividing resources across partitions include a compute sled. The compute sled is to determine partitions among sockets of the compute sled. Each socket is associated with a corresponding processor. The compute sled is also to establish a separate memory space for each determined partition, obtain, from an application executed in one of the sockets, a request to access a logical memory address, identify the partition associated with the memory access request, determine a corresponding physical memory address as a function of the identified partition and the logical memory address, and access a memory of the compute sled at the determined physical memory address. Other embodiments are also described and claimed.

公开(公告)号：US09921997B2

公开(公告)日：2018-03-20

申请号：US15089403

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC: G06F13/42 ,  G06F12/02 ,  G06F13/40 ,  G06F3/06 ,  G06F11/30 ,  G06F11/22

CPC classification number: G06F13/4282 ,  G06F3/0664 ,  G06F3/0688 ,  G06F11/221 ,  G06F11/2221 ,  G06F11/3027 ,  G06F12/0246 ,  G06F13/4022 ,  G06F2212/7201

Abstract: A mechanism for PCIe cable topology discovery in a Rack Scale Architecture (RSA) and associated methods, apparatus, and systems. Pooled system drawers installed in rack are interconnected via multiple PCIe cables coupled to PCIe ports on the pooled system drawers. The PCIe ports are associated with host ports connections between server nodes and host ports in respective pooled system drawers are automatically detected, with corresponding PCIe connection information being automatically generated and aggregated to determine the PCIe cable topology for the rack. In one aspect, PCIe devices are emulated for each host port in a pooled storage drawer including pooled PCIe storage devices. Server nodes in a pooled compute drawer send PCIe configuration messages over the PCIe cables, with returned reply messages generated by the emulated PCIe devices identifying the host ports. Information pertaining to the host ports, pooled system drawers, and server nodes is used to determine the PCIe cable topology.

公开(公告)号：US09864603B2

公开(公告)日：2018-01-09

申请号：US14498092

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Mohan J. Kumar

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/30076 ,  G06F9/30109 ,  G06F9/3861

Abstract: A processor includes a front end including a decoder to decode an instruction, a scheduler to assign execution of the instruction to a core, and a core to execute the instruction. The instruction specifies that interrupts such as corrected machine check interrupts are to be selectively suppressed. The processor further includes an error handling unit including logic to determine that an interrupt caused by an error is to be created and that an error consumer has requested interrupt notification. The error handling unit further includes logic to, based on the instruction specifying that interrupts are to be selectively suppressed, send the interrupt to a producer that issued the instruction rather than the error consumer.

公开(公告)号：US09686143B2

公开(公告)日：2017-06-20

申请号：US14494892

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

IPC: H04L12/24 ,  H04L29/12 ,  H04L12/855

CPC classification number: H04L41/12 ,  H04L41/044 ,  H04L47/2466 ,  H04L61/2015 ,  H04L61/2507

Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

公开(公告)号：US09612887B2

公开(公告)日：2017-04-04

申请号：US14751733

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Vincent J. Zimmer ,  Rajesh Poornachandran

IPC: G06F9/54

CPC classification number: G06F9/544 ,  G06F9/542

Abstract: This disclosure is directed to firmware-related event notification. A device may comprise an operating system (OS) configured to operate on a platform. During initialization of the device a firmware module in the platform may load at least one globally unique identifier (GUID) into a firmware configuration table. When the platform notifies the OS, the firmware module may load at least one GUID into a platform notification table and may set a platform notification bit in a platform notification table status field. Upon detecting the notification, an OS management module may establish a source of the notification by querying the platform notification table. The platform notification bit may cause the OS management module to compare GUIDs in the platform notification table and the firmware configuration table. Services may be called based on any matching GUIDs. If no GUIDs match, the services may be called based on firmware variables in the device.

公开(公告)号：US20160378344A1

公开(公告)日：2016-12-29

申请号：US14748798

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  George Vergis

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/065 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F9/4403 ,  G06F9/4418 ,  G06F11/00 ,  G06F12/0868 ,  G06F13/28 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  Y02D10/13

Abstract: Methods and apparatus for effecting a processor- and platform-assisted NVDIMM solution using standard DRAM and consolidated storage. The methods and apparatus enable selected data in DRAM devices, such as DIMMs to be automatically copied to a persistent storage device such as an SSD in response to detection of a power unavailable event or an operating system error or failure without any operating system intervention. In one aspect, a platform includes a power supply and a temporary power source, such as a capacitor-based energy storage device, a small battery, or a combination of the two, either integrated in the power supply or separate. When power becomes unavailable, the temporary power source is use to continue to provide power to selected components in one or more power protected domains. The energy stored in the temporary power source is sufficient to temporarily power the components to enable DRAM data to be written to the persistent storage device. Upon system restart, the previously-stored DRAM data is restored to one or more DRAM devices from which the data was originally copied.

Abstract translation: 使用标准DRAM和统一存储实现处理器和平台辅助NVDIMM解决方案的方法和设备。 所述方法和装置使得诸如DIMM之类的DRAM设备中的所选数据能够自动复制到诸如SSD的持久存储设备，以响应于检测到不可用电力事件或操作系统错误或故障，而无需任何操作系统干预。 一方面，平台包括集成在电源中或单独的电源和临时电源，诸如基于电容器的能量存储装置，小电池或两者的组合。 当电力不可用时，临时电源用于继续向一个或多个电源保护域中的选定组件供电。 存储在临时电源中的能量足以临时为组件供电，以使DRAM数据能够写入持久存储设备。 在系统重新启动时，先前存储的DRAM数据被恢复到原始复制数据的一个或多个DRAM装置。

公开(公告)号：US20160350002A1

公开(公告)日：2016-12-01

申请号：US14998058

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  James A. McCall ,  Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: G06F3/06

CPC classification number: G06F12/02 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.

Abstract translation: 系统启用存储设备特定的自刷新进入和退出命令。 当共享控制总线（诸如等级上的所有存储设备）中的存储设备进行自刷新时，存储器控制器可以向存储器设备发出具有自刷新退出命令和唯一存储器设备标识符的特定于设备的命令 。 控制器通过共享控制总线发送命令，只有选定的已识别的存储设备将退出自刷新，而其他设备将忽略该命令并保持自刷新。 然后，控制器可以通过共享数据总线与特定存储器设备执行数据访问，而其他存储器件处于自刷新状态。

公开(公告)号：US20160343453A1

公开(公告)日：2016-11-24

申请号：US15226863

申请日：2016-08-02

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

IPC: G11C29/36 ,  G11C29/18 ,  G11C29/44 ,  G11C29/38

CPC classification number: G11C29/36 ,  G11C29/18 ,  G11C29/38 ,  G11C29/44 ,  G11C29/56008

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.