公开(公告)号：US20210397999A1

公开(公告)日：2021-12-23

申请号：US17359395

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned M. Smith ,  Karthik Kumar ,  Sunil Cheruvu

IPC: G06N5/04 ,  G06F11/34 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture to offload execution of a portion of a machine learning model are disclosed. An example apparatus includes processor circuitry to instantiate offload controller circuitry to select a first portion of layers of the machine learning model for execution at a first node and a second portion of the layers for remote execution for execution at a second node, model executor circuitry to execute the first portion of the layers, serialization circuitry to serialize the output of the execution of the first portion of the layers, and a network interface to transmit a request for execution of the machine learning model to the second node, the request including the serialized output of the execution of the first portion of the layers of the machine learning model and a layer identifier identifying the second portion of the layers of the machine learning model.

公开(公告)号：US11196837B2

公开(公告)日：2021-12-07

申请号：US16369384

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Petar Torre ,  Ned Smith ,  Brinda Ganesh ,  Evan Custodio ,  Suraj Prabhakaran

IPC: H04L12/911 ,  H04L29/08 ,  H04L12/66

Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.

公开(公告)号：US11159454B2

公开(公告)日：2021-10-26

申请号：US16748232

申请日：2020-01-21

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Anil Rao ,  Suraj Prabhakaran ,  Mohan Kumar ,  Karthik Kumar

IPC: H04L12/947 ,  H04L12/66 ,  H04L12/801 ,  H04L12/931 ,  H04L12/24

Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.

公开(公告)号：US11115497B2

公开(公告)日：2021-09-07

申请号：US16829814

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Slawomir Putyrski ,  Susanne M. Balle ,  Thomas Willhalm ,  Karthik Kumar

IPC: H04L29/08 ,  H04L12/911

Abstract: Technologies for providing advanced resource management in a disaggregated environment include a compute device. The compute device includes circuitry to obtain a workload to be executed by a set of resources in a disaggregated system, query a sled in the disaggregated system to identify an estimated time to complete execution of a portion of the workload to be accelerated using a kernel, and assign, in response to a determination that the estimated time to complete execution of the portion of the workload satisfies a target quality of service associated with the workload, the portion of the workload to the sled for acceleration.

公开(公告)号：US11095755B2

公开(公告)日：2021-08-17

申请号：US15645516

申请日：2017-07-10

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Rahul Khanna ,  Karthik Kumar

IPC: H04L29/04 ,  H04L29/08 ,  G06F11/36 ,  H04L12/24

Abstract: A host fabric interface (HFI), including: first logic to communicatively couple a host to a fabric; and second logic to provide a disaggregated telemetry engine (DTE) to: receive notification via the fabric of available telemetry data for a remote accelerator; allocate memory for handling the telemetry data; and receive the telemetry data from the disaggregated accelerator.

公开(公告)号：US10986005B2

公开(公告)日：2021-04-20

申请号：US15638855

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Rahul Khanna ,  Sujoy Sen ,  Karthik Kumar

IPC: H04L12/26 ,  G06F16/901 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L12/24 ,  H04L12/931 ,  H04L12/947 ,  H04L29/08 ,  H04L29/06 ,  H04Q11/00 ,  H05K7/14 ,  G06F9/38 ,  G06F9/50 ,  H04L12/851 ,  H04L12/811 ,  H05K5/02 ,  H04W4/80 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04 ,  H04L12/911 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933

Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

公开(公告)号：US10969975B2

公开(公告)日：2021-04-06

申请号：US16529533

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  John Chun Kwok Leung ,  Mark Schmisseur ,  Thomas Willhalm

IPC: G06F3/06 ,  G06F9/50

Abstract: The present disclosure relates to a dynamically composable computing system comprising a computing fabric with a plurality of different disaggregated computing hardware resources having respective hardware characteristics. A resource manager has access to the respective hardware characteristics of the different disaggregated computing hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated computing hardware resources with respective hardware characteristics meeting requirements of an application to be executed on the composite computing node. An orchestrator is configured to schedule the application using the assembled composite computing node.

公开(公告)号：US10951516B2

公开(公告)日：2021-03-16

申请号：US16291541

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Brian J. Slechta

IPC: H04L12/725 ,  H04L12/803 ,  H04L12/933 ,  H04L12/825 ,  H04L12/931

Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.

公开(公告)号：US10944689B2

公开(公告)日：2021-03-09

申请号：US16024465

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Mark A. Schmisseur ,  Timothy Verrall

IPC: G06F15/173 ,  H04L12/919 ,  H04L12/911 ,  G06F9/50 ,  G06N20/00

Abstract: There is disclosed in one example a communication apparatus, including: a telemetry interface; a management interface; and an edge gateway configured to: identify diverted traffic, wherein the diverted traffic includes traffic to be serviced by an edge microcloud configured to provide a plurality of services; receive telemetry via the telemetry interface; use the telemetry to anticipate a future per-service demand within the edge microcloud; compute a scale for a resource to meet the future per-service demand; and operate the management interface to instruct the edge microcloud to perform the scale before the future per-service demand occurs.

公开(公告)号：US10747691B2

公开(公告)日：2020-08-18

申请号：US15949095

申请日：2018-04-10

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: G06F13/16 ,  G06F9/38 ,  G06F9/30 ,  G06N20/00

Abstract: Examples provide a memory device, a dual inline memory module, a storage device, an apparatus for storing, a method for storing, a computer program, a machine readable storage, and a machine readable medium. A memory device is configured to store data and comprises one or more interfaces configured to receive and to provide data. The memory device further comprises a memory module configured to store the data, and a memory logic component configured to control the one or more interfaces and the memory module. The memory logic component is further configured to receive information on a specific memory region with one or more model identifications, to receive information on an instruction to perform an acceleration function for one or more certain model identifications, and to perform the acceleration function on data in a specific memory region with the one or more certain model identifications.