中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

96 records (took 0.032 seconds)

    Disaggregated computing for distributed confidential computing environment
    2.
    发明授权
    Disaggregated computing for distributed confidential computing environment 有权

    公开(公告)号：US12033005B2

    公开(公告)日：2024-07-09

    申请号：US17532562

    申请日：2021-11-22

    Applicant: Intel Corporation

    Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

    IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

    CPC classification number: G06F9/5083 ,  G06F9/3814 ,  G06F9/5027 ,  G06T1/20 ,  G06T1/60

    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a programmable integrated circuit (IC) comprising secure device manager (SDM) hardware circuitry to: receive a tenant bitstream of a tenant and a tenant use policy for utilization of the programmable IC via the tenant bitstream, wherein the tenant use policy is cryptographically bound to the tenant bitstream by a cloud service provider (CSP) authorizing entity and signed with a signature of the CSP authorizing entity; in response to successfully verifying the signature, extract the tenant use policy to provide to a policy manager of the programmable IC for verification; in response to the policy manager verifying the tenant bitstream based on the tenant use policy, configure a partial reconfiguration (PR) region of the programmable IC using the tenant bitstream; and associate a slot ID of the PR region with the tenant use policy.

    Disaggregated rack mount storage side transaction support
    4.
    发明授权
    Disaggregated rack mount storage side transaction support 有权

    公开(公告)号：US11550617B2

    公开(公告)日：2023-01-10

    申请号：US16907927

    申请日：2020-06-22

    Applicant: Intel Corporation

    Inventor： Arun Raghunath ,  Yi Zou ,  Tushar Sudhakar Gohad ,  Anjaneya R. Chagam Reddy ,  Sujoy Sen

    IPC: G06F9/46 ,  G06F3/06

    Abstract: A method is described. The method includes performing the following with a storage end transaction agent within a storage sled of a rack mounted computing system: receiving a request to perform storage operations with one or more storage devices of the storage sled, the request specifying an all-or-nothing semantic for the storage operations; recognizing that all of the storage operations have successfully completed; after all of the storage operations have successfully completed, reporting to a CPU side transaction agent that sent the request that all of the storage operations have successfully completed.

    DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT
    6.
    发明申请
    DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT 有权

    公开(公告)号：US20220100584A1

    公开(公告)日：2022-03-31

    申请号：US17532569

    申请日：2021-11-22

    Applicant: Intel Corporation

    Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

    IPC: G06F9/50 ,  G06T1/60 ,  G06T1/20 ,  G06F9/38

    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a programmable integrated circuit (IC) comprising system manager hardware circuitry to: interface, over a network, with a remote application of a client platform, the system manager hardware circuitry to interface with the remote application using a message-based interface; perform resource management of resources of the programmable IC; validate incoming messages to the programmable IC; verify whether a requester is allowed to perform requested actions of the incoming messages that are successfully validated; and manage transfer of data between the programmable IC and the remote application based on successfully verifying the requester.

    Technologies for remote networked accelerators
    7.
    发明授权
    Technologies for remote networked accelerators 有权

    公开(公告)号：US10970246B2

    公开(公告)日：2021-04-06

    申请号：US16402507

    申请日：2019-05-03

    Applicant: Intel Corporation

    Inventor： Paul H. Dormitzer ,  Susanne M. Balle ,  Sujoy Sen ,  Evan Custodio

    IPC: G06F15/16 ,  G06F15/173 ,  G06F13/42

    Abstract: Technologies for network interface controllers (NICs) include a computing device having a NIC coupled to a root FPGA via an I/O link. The root FPGA is further coupled to multiple worker FPGAs by a serial link with each worker FPGA. The NIC may receive a remote direct memory access (RDMA) message from a remote host and send the RDMA message to the root FPGA via the I/O link. The root FPGA determines a target FPGA based on a memory address of the RDMA message. Each FPGA is associated with a part of a unified address space. If the target FPGA is a worker FPGA, the root FPGA sends the RDMA message to the worker FPGA via the corresponding serial link, and the worker FPGA processes the RDMA message. If the root FPGA is the target, the root FPGA may process the RDMA message. Other embodiments are described and claimed.

    TECHNOLOGIES FOR ESTABLISHING COMMUNICATION CHANNEL BETWEEN ACCELERATOR DEVICE KERNELS
    9.
    发明申请
    TECHNOLOGIES FOR ESTABLISHING COMMUNICATION CHANNEL BETWEEN ACCELERATOR DEVICE KERNELS 审中-公开

    公开(公告)号：US20200004712A1

    公开(公告)日：2020-01-02

    申请号：US16236255

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Susanne M. Balle ,  Evan Custodio ,  Francesc Guim Bernat ,  Sujoy Sen ,  Slawomir Putyrski ,  Paul Dormitzer ,  Joseph Grecco

    IPC: G06F13/40 ,  G06F13/36

    Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

    TECHNOLOGIES FOR PROVIDING EFFICIENT DISTRIBUTED DATA STORAGE IN A DISAGGREGATED ARCHITECTURE
    10.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT DISTRIBUTED DATA STORAGE IN A DISAGGREGATED ARCHITECTURE 审中-公开

    公开(公告)号：US20190042091A1

    公开(公告)日：2019-02-07

    申请号：US15922502

    申请日：2018-03-15

    Applicant: Intel Corporation

    Inventor： Arun Raghunath ,  Anjaneya Reddy Chagam Reddy ,  Sujoy Sen ,  Yi Zou

    IPC: G06F3/06 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16

    Abstract: Technologies for providing efficient distributed data storage in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to receive, through a network and with the network interface controller, a data access request from a compute device. The data access request includes a data payload indicative of an object to be stored. The circuitry is also to map the object to a set of multiple data storage sleds for distributed storage of the object. Additionally, the circuitry is to send a write request with the object and an object identifier to the mapped data storage sleds to store the object in one or more data storage devices located on each data storage sled and concurrently send metadata without the object to one or more other compute sleds associated with the mapped data storage sleds. Other embodiments are also described and claimed.

Patent Agency Ranking