公开(公告)号：WO1996029738A1

公开(公告)日：1996-09-26

申请号：PCT/US1996003538

申请日：1996-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ROBERTS, Martin, Ceredig

IPC: H01L27/11

CPC classification number: H01L28/20 ,  H01L27/0802 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904 ,  Y10S438/979

Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the spacer outer surface; g) providing a conformal layer of a semiconductive material over the exposed outer spacer surface and over the inner spacer surface, the conformal layer making electrical connection with the node; and h) patterning the conformal layer into a desired resistor shape. SRAM and other integrated circuitry incorporating this and other resistors is disclosed.

Abstract translation: 从半导体材料形成电阻器的半导体处理方法包括：a）提供与电阻器进行电连接的节点; b）在节点外部提供第一电绝缘材料; c）在所述节点外部的所述第一电绝缘材料中提供暴露的垂直侧壁; d）在所述第一材料的外部和所述第一材料垂直侧壁上方提供第二电绝缘材料，所述第一和第二材料可相对于彼此选择性地蚀刻; e）相对于所述第一材料选择性地各向异性地蚀刻所述第二材料，以在所述第一材料垂直侧壁上方形成基本上垂直延伸的侧壁隔离物，并且向外暴露所述邻近所述侧壁间隔物的所述第一材料，所述间隔件具有内表面和外表面; f）相对于第二材料选择性地蚀刻第一材料以向外暴露间隔件外表面的至少一部分; g）在所述暴露的外隔离物表面上并在所述内间隔件表面上提供半导体材料的保形层，所述共形层与所述节点形成电连接; 以及h）将所述保形层图案化成所需的电阻器形状。 公开了SRAM和其它集成电路的集成电路。

公开(公告)号：WO1996027208A1

公开(公告)日：1996-09-06

申请号：PCT/US1996002413

申请日：1996-02-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MCCLURE, Brent, A. ,  NEW, Daryl, C.

IPC: H01L21/8242

CPC classification number: H01L28/40 ,  H01L21/32131 ,  H01L28/91

Abstract: A method is described for forming a structure by redepositing a starting material (5) on sidewalls of a foundation (15) during an etch of the starting material. The starting material can be a layer of conductive material formed into an electrode of a capacitor. Multiple layers of conductive material (50, 55) and dielectric material (60) can be etched to form a multilayered structure, such as a capacitor.

Abstract translation: 描述了一种通过在起始材料的蚀刻期间将起始材料（5）重新沉积在基础（15）的侧壁上来形成结构的方法。 起始材料可以是形成电容器的电极的导电材料层。 多层导电材料（50,55）和电介质材料（60）可以被蚀刻以形成诸如电容器的多层结构。

公开(公告)号：WO1996026544A1

公开(公告)日：1996-08-29

申请号：PCT/US1996001841

申请日：1996-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  JOST, Mark ,  DENNISON, Charles, H. ,  PAREKH, Kunal

IPC: H01L27/108

CPC classification number: H01L27/10844 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor memory devices and methods for forming the devices are disclosed. In one embodiment, the devices include a) a semiconductor substrate (11); b) a field effect transistor gate (14) positioned outwardly of the semiconductor substrate; c) opposing active areas (24, 26) formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node (36), a capacitor dielectric layer (38), and an outer cell node (40); the inner storage node electrically connecting with the one active area and physically contacting the one active area; e) a bit line (46); f) a dielectric insulating layer (44) positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug (36, 38, 40, 39) extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area. Constructions in which the bit line plug comprises an electrically conductive annular ring are also disclosed.

Abstract translation: 公开了用于形成器件的半导体存储器件和方法。 在一个实施例中，器件包括a）半导体衬底（11）; b）位于半导体衬底外侧的场效应晶体管栅极（14）; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区（24,26）; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点（36），电容器介电层（38）和外部单元节点（40）; 所述内部存储节点与所述一个活动区域电连接并物理接触所述一个活动区域; e）位线（46）; f）位于位线和另一个有效区域之间的介电绝缘层（44）; 以及g）延伸穿过所述绝缘层的导电位线插头（36,38,40,39）以与所述另一个有源区域接触并将所述位线与所述另一个有源区域电互连。 还公开了位线插头包括导电环形圈的结构。

公开(公告)号：WO1996026519A1

公开(公告)日：1996-08-29

申请号：PCT/US1996002023

申请日：1996-02-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  PAWLOWSKI, Joseph, Thomas

IPC: G11C07/00

CPC classification number: G11C11/419 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22

Abstract: A synchronous SRAM module comprises first and second SRAM chips. Each SRAM chip has three chip enable inputs. A module enable and memory selection circuit is coupled to the two SRAM chips to perform the dual tasks of (1) selectively enabling or disabling both SRAM chips and (2) choosing either the first or second SRAM chips for access. The SRAM module can also be placed in a pipelining mode where external signals from a microprocessor are ignored to facilitate internal operation, such as burst reads. A synchronous burst SRAM device employed in the SRAM module is also described.

Abstract translation: 同步SRAM模块包括第一和第二SRAM芯片。 每个SRAM芯片都有三个芯片使能输入。 模块使能和存储器选择电路耦合到两个SRAM芯片，以执行以下两项任务：（1）选择性地启用或禁用SRAM芯片，以及（2）选择第一或第二SRAM芯片进行访问。 SRAM模块也可以放置在流水线模式中，其中来自微处理器的外部信号被忽略以便于内部操作，例如突发读取。 还描述了在SRAM模块中采用的同步突发SRAM器件。

公开(公告)号：WO1996020481A1

公开(公告)日：1996-07-04

申请号：PCT/US1995016808

申请日：1995-12-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MERRITT, Todd, A. ,  MANNING, Troy, A.

IPC: G11C07/00

CPC classification number: G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/407

Abstract: An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

Abstract translation: 集成电路存储器件被设计为执行高速数据写入周期。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问的开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问并初始化设备以进行另一脉冲串访问。 写周期时间最大化，以允许突发模式工作频率的增加。 阵列读出放大器附近的局部逻辑门用于控制写入数据驱动器，以提供最大写入时间，而不会在输入/输出线路平衡周期内交叉电流。 通过在数据检测放大器位置局部地选通具有全局平衡信号的全局写使能信号，提供本地写周期控制信号，其基本上对整个周期时间有效，减去突发存取存储器件中的I / O线平衡周期。 对于诸如EDO和快速页面模式的非突发模式存储器件，写入功能可以在平衡周期结束后立即开始，以提供最大写入时间，而不会干扰下一个访问周期的地址建立时间。

公开(公告)号：WO1996014663A1

公开(公告)日：1996-05-17

申请号：PCT/US1995014568

申请日：1995-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  FIGURA, Thomas, A. ,  PRALL, Kirk, D.

IPC: H01L29/02

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method of forming a contact area between two vertical structures. A first layer of material conforming to and extending between vertical sidewalls is covered with a mask layer. The mask layer is patterned and etched to remove the horizontal region of the mask layer between the vertical sidewalls, thereby exposing the first layer of material at the desired location of the contact area, while retaining at least a portion of the vertical regions of the mask layer. Using the remaining vertical regions off the mask layer as an etch mask, the exposed portions of the first layer are then etched away to form the contact area. Another aspect of the invention provides a method of making a DRAM that utilizes a capacitor insulating layer over the capacitor second conductor (or cell poly) to self-align the bit line contact to the capacitor second conductor. In accordance with this aspect of the invention, a capacitor is formed over a semiconductor wafer. The capacitor includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. A capacitor insulating layer is formed on the second conductor. The capacitor insulting layer is patterned and etched to expose portions of the second conductor at the desired location of the bit line contact. Then, using the capacitor insulating layer as a hard mask, the exposed portions of the second conductor are etched away in the area in which the bit line contact will subsequently be formed.

Abstract translation: 一种在两个垂直结构之间形成接触区域的方法。 符合并在垂直侧壁之间延伸的第一材料层被掩模层覆盖。 掩模层被图案化和蚀刻以去除垂直侧壁之间的掩模层的水平区域，从而将第一层材料暴露在接触区域的期望位置处，同时保留掩模的垂直区域的至少一部分 层。 使用离开掩模层的剩余垂直区域作为蚀刻掩模，然后蚀刻掉第一层的暴露部分以形成接触面积。 本发明的另一方面提供了一种制造DRAM的方法，该DRAM利用电容器第二导体（或电池多晶硅）上的电容绝缘层将位线接触自对准到电容器第二导体。 根据本发明的该方面，在半导体晶片上形成电容器。 电容器包括第一导体，第一导体上的电介质层和介电层上的第二导体。 在第二导体上形成电容绝缘层。 对电容器绝缘层进行图案化和蚀刻，以在位线接触的期望位置处露出第二导体的部分。 然后，使用电容器绝缘层作为硬掩模，在随后将形成位线接触的区域中蚀刻掉第二导体的暴露部分。

公开(公告)号：WO1992003777A1

公开(公告)日：1992-03-05

申请号：PCT/US1991005885

申请日：1991-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HESSON, James, H.

IPC: G06F03/00

CPC classification number: G06F9/30043 ,  G06F9/3836 ,  G06F9/3838

Abstract: A block transfer register scoreboard unit (16) for data processing systems that not only minimizes no-operation (NOP) instructions, but also permits the processor's register file (14) to be operated as a double-buffered memory, with the processor's execution unit (15) processing one block of registers in the register file (14) simultaneously with the data load-store unit (17) performing a memory-to-register file transfer operation. Scoreboard unit architecture supports both block transfer load operations, as well as those of the single transfer load type. Such an architecture permits block transfer data load and store operation, as well as execution unit or program control unit instructions to operate in parallel, thus permitting a high-speed data processor to execute multiple instructions during a single machine clock cycle. The scoreboard unit (16) is sufficiently compact to enable implementation on a microprocessor chip.

Abstract translation: 一种用于数据处理系统的块传输寄存器记分板单元（16），其不仅使无操作（NOP）指令最小化，而且还允许处理器的寄存器文件（14）作为双缓冲存储器操作，其中处理器的执行单元 （15）与执行存储器到寄存器文件传送操作的数据加载存储单元（17）同时处理寄存器文件（14）中的一个寄存器块。 记分板单元架构支持块传输负载操作以及单次传输负载类型。 这种架构允许块传输数据加载和存储操作，以及执行单元或程序控制单元指令并行操作，从而允许高速数据处理器在单个机器时钟周期期间执行多个指令。 记分板单元（16）足够紧凑以使得能够在微处理器芯片上实现。

公开(公告)号：WO1991019249A1

公开(公告)日：1991-12-12

申请号：PCT/US1991000823

申请日：1991-02-06

Applicant: MICRON TECHNOLOGY, INC. ,  HESSON, James

Inventor： MICRON TECHNOLOGY, INC.

IPC: G06F07/52

CPC classification number: G06F7/5443

Abstract: A high-speed circuit that performs unsigned mode, two's complement mode, and two types of mixed mode multiplication-accumulation with equal facility. The circuit is an array (10) constructed from ten different adder elements (FA1S, FA1A, FA2A, FAC, FACA, FACC, FAAC, FAAC3, HAC, and HAC2, which correspond to Figures 13-22, respectively). The array has two multiplier input operands (X and Y) and one accumulator term (Z), the three of which may be expressed as binary power expansions. Final addition of sumout and carryout terms of the array (10) is performed by final adder (11), which may comprise any of several possible adder configurations, including full carry lookahead, carry select, and conditional-sum type adders. Speed is accomplished through the use of high-speed adder elements having few gate delays, and by summing all even array rows together and all odd rows together, then adding the even sum with the odd sum in the final adder (11) using a Wallace tree technique. The circuit incorporates a high degree of regularity and interconnectivity, which facilitates compact circuit layout.