公开(公告)号：JPH09297753A

公开(公告)日：1997-11-18

申请号：JP10915796

申请日：1996-04-30

Applicant: SONY CORP

Inventor： OZAKI YASUNARI ,  ITO YASU ,  IKEDA YASUNARI

IPC: G06F17/14

Abstract: PROBLEM TO BE SOLVED: To enable faster arithmetic operation. SOLUTION: Inputted data are supplied to a terminal in0 or in1 of a butterfly computing element 4 through a selector 2 and a selector 3. The butterfly computing element 4 performs butterfly operation for the data inputted from the terminals in0 and in1, by using a rotational operator stored in a ROM 5 and outputs the result from terminals out0 and out1. Then a selector 6 alternately selects the data outputted from the terminals out0 and out1 and supplies them to a selector 7. The selector 7 outputs the data to a selector 22, if the butterfly operation is not yet completed. The selector 22 supplies the data to memories 8 and 23, alternately. The data written in the memory 8 are read out alternately through a selector 21 and inputted to the butterfly computing element 4 again, through the selector 2 and selector 3.

公开(公告)号：JPH09233138A

公开(公告)日：1997-09-05

申请号：JP3453796

申请日：1996-02-22

Applicant: SONY CORP

Inventor： IKEDA TAMOTSU ,  IKEDA YASUNARI ,  OKADA TAKAHIRO

IPC: H04L27/18 ,  H03M13/23 ,  H04L1/00 ,  H04L27/233

Abstract: PROBLEM TO BE SOLVED: To improve error correction performance and to reduce the circuit scale of a differential demodulation circuit. SOLUTION: Let complex input data be (a+jb) and (c+jd), then real number multipliers 31 to 34 calculate ac, ad, bc, bd, an adder 35 calculates (ac+bd) and a subtractor 36 calculates (bc-ad). Thus, a differential demodulation result Y(t)=(ac+bd)-j(bc-ad) is obtained. This refers to a multiple of square of a transmission line characteristics with a conventional differential demodulation result, then the result has immunity to disturbance such as fading or phase noise.

公开(公告)号：JPH08251136A

公开(公告)日：1996-09-27

申请号：JP4851595

申请日：1995-03-08

Applicant: SONY CORP

Inventor： IKEDA YASUNARI ,  MOMOSHIRO TOSHIHISA ,  ITO YASU ,  MIYATO YOSHIKAZU

IPC: H04J11/00

Abstract: PURPOSE: To speedily and easily reproduce a carrier and a clock on a reception side by transmitting the carrier of a frequency which is not used for the transmission of an information system and in which one-to-integer time of a second period becomes a period as a reference. CONSTITUTION: The respective carriers of an orthogonal frequency division multiplex system(OFDM) correspond to the coefficient numbers '0' to '23' of a discrete Fourier transformer(DFT). Data '0' is allocated to the coefficient numbers 0, 2, 20, 22 and 23 so as to prevent outputs from being actually emitted. Actual transmission information are allocated to DFT coefficient numbers '3' to '19' and DFT coefficient numbers '1' and '21' are set to be carriers f1 and f21 for reference for carrier reproduction and clock reproduction. The carriers which are not used for the transmission of the information system among the carriers of the frequency in which one-to-integer time of a guard interval becomes one period are used for the carriers f1 and f2 .

公开(公告)号：JPH0897731A

公开(公告)日：1996-04-12

申请号：JP22546094

申请日：1994-09-21

Applicant: SONY CORP

Inventor： IKEDA YASUNARI ,  IKEDA TAMOTSU ,  MIYATO YOSHIKAZU

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/27 ,  H04B14/04 ,  H03M13/22

Abstract: PURPOSE: To extend spread interval of received data without increasing the circuit scale of a memory. CONSTITUTION: In the interleave system where two sets of memories 100, 200 are controlled in a way that reading of one memory and write of the other memory are alternate conversely conducted, input data are written sequentially and continuously in the row direction of a storage cell array to the memory in the write mode, similar write operation is sequentially progressed as to its adjacent row when the write of the former row is finished, data are read sequentially and continuously in the column direction of the storage cell array of the other memory in the read mode and when data of the row are all read, a column to be read in a discontinuous order according to a predetermined rule is selected and similar read is promoted sequentially to selected columns.

公开(公告)号：JPH0832457A

公开(公告)日：1996-02-02

申请号：JP16915094

申请日：1994-07-21

Applicant: SONY CORP

Inventor： IKEDA TAMOTSU ,  IKEDA YASUNARI ,  OKADA TAKAHIRO

IPC: G06F11/10 ,  H03M13/23 ,  H04L1/00 ,  H04L25/08 ,  H04L27/00 ,  H04L27/38 ,  H03M13/12

Abstract: PURPOSE:To simplify the configuration, to reduce the circuit scale and the cost. CONSTITUTION:An I component Sii at a hypothetical signal point is subtracted from an I signal corresponding to a reception signal point at a subtractor circuit 71, its output (I-Sii) is outputted to a mixer 73 as it is and high-order k-bits are selected by a bit selection circuit 81 and outputted to the mixer 73. Data in n-bit and data in k-bit are multiplied in the mixer 73 to provide an output of data in (n+k) bits. The configuration of the mixer 73 is simplified by reducing one of data to be squared substantially from n-bit into k-bit.

公开(公告)号：JPH06232923A

公开(公告)日：1994-08-19

申请号：JP1853193

申请日：1993-02-05

Applicant: SONY CORP

Inventor： IKEDA YASUNARI

IPC: H04L25/08 ,  H03M13/23 ,  H03M13/41 ,  H04L27/00 ,  H04L27/38

Abstract: PURPOSE:To obtain the Viterbi decoder in which the processing time is quickened and the circuit scale is reduced. CONSTITUTION:ROMs 201-299 of a branch metric circuit 30 apply processing to prescribed sets of parallel paths. The ROMs 201-299 output predetermined selection paths S201a-299a and branch metrics BM201b-299b of a reception signal about the selected paths to registers 301-399 among prescribed sets of parallel paths according to (I,Q) coordinates indicated by a reception I signal S14a and a reception Q signal S14b. The registers 301-399 store tentatively signals from the ROMs 201-299 and output them to an ACS circuit.

公开(公告)号：JPH0614689B2

公开(公告)日：1994-02-23

申请号：JP11326190

申请日：1990-04-28

Applicant: SONY CORP

Inventor： OKADA TAKAFUMI ,  IKEDA YASUNARI ,  MATSUNAGA OSAMU

IPC: H04N3/16 ,  H04N5/44 ,  H04N7/01

公开(公告)号：JPH0588598B2

公开(公告)日：1993-12-22

申请号：JP13548783

申请日：1983-07-25

Applicant: SONY CORP

Inventor： NAKANO HIROSHI ,  IKEDA YASUNARI

IPC: H04N11/20

公开(公告)号：JPH05252052A

公开(公告)日：1993-09-28

申请号：JP4572992

申请日：1992-03-03

Applicant: SONY CORP

Inventor： IKEDA YASUNARI ,  TOGASHI HARUO

IPC: H03M7/42

Abstract: PURPOSE:To set an output data width to be an optional width by using a shifter with a small data width. CONSTITUTION:A coding input accesses a coding table 3 storing a variable length code, a code length and a control flag for coding control via a buffer memory 2. A control flag output from the coding table 3 is connected to a read control terminal of the buffer memory 2 and an input of the coding table, the variable length code is inputted to a barrel shifter 4, high-order 16-bits are inputted to a register 6 via a gate circuit 5 and low-order 16-bits are inputted directly to a register 7. A multiplexer 8 selects an output from the register 6 or an output of the register 7 and feeds back the selected output to the gate circuit 5. When the data of 16-bits or mote are stored in the registers 6, 7, the high-order data of the register 6 are written in a speed smoothing output buffer memory 9 and the multiplexer 8 selects the register 7 to feed back the low-order data excluding the high-order data to the gate circuit 5 and outputs the result through sequential coding.

公开(公告)号：JPH0590976A

公开(公告)日：1993-04-09

申请号：JP25136891

申请日：1991-09-30

Applicant: SONY CORP

Inventor： IKEDA YASUNARI

IPC: H03M7/42

Abstract: PURPOSE:To provide flexibility by using a shifter with a small data width and selecting an output data width to be an optional width. CONSTITUTION:A coding input accesses a coding table 3 in which a variable length and its code length are stored via a buffer memory 2. The variable length code is inputted to a barrel shifter 4, high-order 17 bits are fed to a register 6 via a gate circuit 5 and low-order 16 bits are directly inputted to a register 7. Moreover, the output 17-bits of the register 6 and the output 16-bits of the register 7 are switched by a multiplexer 8 and the selected output is fed back to the gate circuit 5 and synthesized. When the data of 16-bits or over are stored in the registers 6, 7, the high-order 16 bits of the register 6 are written in a speed smoothing output buffer 9 and the multiplexer 8 selects the register 7 so as to feed back low-order data except the high-order 16 bits to the gate circuit 5 and the data are sequentially coded and outputted.