公开(公告)号：EP0098082A3

公开(公告)日：1986-05-07

申请号：EP83303488

申请日：1983-06-16

Applicant: SONY CORPORATION

Inventor： Creed, David Morris ,  Ive, John Goodwin Spencer

IPC: G11B05/09 ,  H04L01/10

CPC classification number: G11B20/1809

Abstract: @ A method of detecting and correcting errors in digital audio signals comprises assembling digital data words each of which corresponds to a digital audio signal representing an analog audio sample into units of six data words, assembling with each unit six redundant words derived by exclusive-OR operations on the data word in each row and each column of the unit, assembling the data words and redundant words into sub-blocks and adding cyclic redundancy check code words to the sub-block, recording and reproducing each sub-block, after reproduction using the code words of each sub-block to add error flags to each word in the sub-block, re-forming the units and assembling with each reproduced unit syndromes derived by exclusive-OR operations on the data words and redundant words in each row in each column of the unit, comparing the syndromes and correcting the error flags in dependence on this comparison, deriving horizontal syndromes by exclusive-OR operations on the data words and redundant words in each row of the reproduced unit and where there is only a single word in a row flagged as being in error, correcting that error word using the horizontal syndrome, and deriving vertical syndromes by exclusive-OR operations on the data words and the redundant word in each column of the reproduced unit and where there is only a single word in that column in error, correcting that error word using the vertical syndrome.

公开(公告)号：EP0131823A3

公开(公告)日：1985-11-06

申请号：EP84107581

申请日：1984-06-29

Applicant: Bauer, Norbert, Dr.-Ing.

Inventor： Bauer, Norbert, Dr.-Ing.

IPC: G11B05/09

CPC classification number: G11B20/1492 ,  G11B20/14

Abstract: Beschrieben wird eine Einrichtung zur Aufzeichnung binärer Signale auf einem magnetischen Informationsträger bei der an einem Aufzeichnungs-Magnetkopf bei jeder Ände rung der aufzuzeichnenden Signale von "0" auf "1" ein Nadel impuls der einen Polarität und bei jeder Änderung von "1" auf "0" ein Nadelimpuls der anderen Polarität angelegt wird.
Die Einrichtung weist entweder zwei Monoflops oder ein Monoflop auf.
Die Ausgangssignale der beiden Monoflops werden über eine Summationsschaltung am Magnetkopf angelegt, wahr end das Ausgangssignal des einen Monoflops über eine Logi kschaltung an den Magnetkopf angelegt wird, die die Stromr ichtung entsprechend dem anliegenden Datensignal umke hrt.
Weiter wird eine Einrichtung zur Rückgewinnung von auf einem magnetischen Informationsträger aufgezeichnet binä ren Signalen beschrieben, die den Nulldurchgang des Lesesi gnals ermittelt. Die Einrichtung weist drei Komparatoren auf, die das Lesesignal mit vorgegebenen Schwellenspannungen vergleichen. Nur wenn die Ausgangssignale der Komparato ren in einer bestimmten Reihenfolge auftreten, wird ein erhal tenes Signal als Lesesignal indentifiziert.

公开(公告)号：EP0084952A3

公开(公告)日：1985-06-26

申请号：EP83300265

申请日：1983-01-19

Applicant: SONY CORPORATION

Inventor： Watanabe, Tetsu c/o Patent Division ,  Tanaka, Masato c/o Patent Division

IPC: G11B05/09

CPC classification number: G11B20/1204 ,  G11B20/1202 ,  G11B20/1809 ,  G11B27/032 ,  G11B27/036 ,  G11B27/3027 ,  G11B27/36 ,  G11B2020/183

Abstract: Apparatus for recording a new digital signal in a track on a magnetic record medium which has a previously recorded digital signal in the track, the digital signal being arranged in data blocks each containing a sync signal, a data signal, an error correction code signal, and an error detection code signal, comprises reproducing means which reproduces each digital signal recorded on the magnetic record medium, a code generating means (8, 9) which supplies a discriminating code signal for each of the data blocks, and recording means (7, HR) which re-records the new digital signal and the respective discriminating code signals in the track on the magnetic record medium.

公开(公告)号：EP0084358A3

公开(公告)日：1985-01-09

申请号：EP83100299

申请日：1983-01-14

Applicant: TANDBERG DATA A/S

Inventor： Lia, Herman

IPC: G11B05/09 ,  H03K05/153

CPC classification number: G11B20/10212 ,  H03K5/1532

Abstract: Bei dem Verfahren werden die von einem Lesekopf (K) eines Magnetschichtspeichers abgegebenen Lesesignale (L) zunächst in an sich bekannter Weise verstärkt und differen ziert. Wenn die differenzierten Lesesignale (L2) in den Nulldurchgängen eine genügende Steigung aufweisen, wer den an den Nulldurchgängen Datenimpulse (D) erzeugt. Die Überprüfung der Steigung erfolgt durch eine nochmalige Differentation der differenzierten Lesesignale (L2) und durch eine Überprüfung, ob diese zweifach differenzierten Lesesig nale (L3) vorgegebene Schwellenspannungen (5) über- oder unterschreiten.

Abstract translation: 该方法包括以已知方式首先放大和微分由磁存储介质的读取头（K）发射的读取信号（L）。 如果差分读信号（L2）的斜率在它们交叉零的点处足够陡，则在过零点产生数据脉冲（D）。 通过差分读取信号（L2）的进一步分化以及通过检查这些两倍分辨的读取信号（L3）是否超过预定的阈值电压（S）来检查斜率。

公开(公告)号：EP0096109A3

公开(公告)日：1984-10-24

申请号：EP82109564

申请日：1982-10-15

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Nagumo, Masahide ,  Inagawa, June ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/151 ,  G06F7/724 ,  G06F7/726 ,  G11B20/1809

Abstract: An error correcting system uses an error location polynominal defined by double correction BCH codes each consisting of the elements of Galois field GF(2m), thereby to generate error locations σ 1 and σ 2 and error patterns e, and e 2 . The system has a first data processing system (401) for performing only additions and multiplications to generate error locations σ 1 and σ 2 and a second data processing system (402) for performing only additions and mutiplica- tions to generate error patterns e 1 and e 2 . The first data processing system (401) comprises a syndrome generator (41), a memory (43), an arithmetic logic unit (44), registers (45A) to (45C), latch circuits (46A) to (46F), registers (47A) to (47F), adder circuits (48A) and (48B) and a zero detector (49). The second data processing system (402) comprises a gate circuit (50), latch circuits (46H) and (46G), an arithmetic logic unit (44), registers (45A) to (45C) and a memory (43).

公开(公告)号：EP0096165A3

公开(公告)日：1984-10-17

申请号：EP83102308

申请日：1983-03-09

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Inagawa, Jun ,  Nagumo, Masahide ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: G06F7/726 ,  G06F1/0307 ,  G11B20/1809 ,  H03M13/15

Abstract: Data representing one element α i of a Galois field GF(2 m ) are stored in a first linear shift register (52), and data representing another element α j of the Galois field GF(2 m ) are stored in a second linear shift register (53). 2 m elements of Galois field GF(2 m ) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter (51) which includes a decoder (511) and an encoder (512). The data representing element α j are supplied from the second linear shift register (53) to the decoder (511). If the data representing the reciprocal of element α j are stored in the converter (51), they are read from the encoder (512). If they are not stored in the converter (51), the first linear shift register (52) and the second linear shift register (63) are shifted N times by control pulses generated by a NOR gate (NOR,) and an AND gate (AND, o ) until any one of the reciprocal data are read from the encoder (512), whereby the register (52) supplies data representing α i+N and the register (53) supplies data representing α -(j+N) . A multiplier (54) multiplies element α i by reciprocal α j or multiplies element α 1+N by reciprocal α -(j+N) , thereby performing the division: a i ÷ α j (= α i-j ).

公开(公告)号：EP0096163A3

公开(公告)日：1984-10-17

申请号：EP83102173

申请日：1983-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Inagawa, Jun ,  Nagumo, Masahide ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/15 ,  G06F7/726 ,  G11B20/1809

Abstract: An apparatus divides one element a' of a Galois field GF(2 m ) by another element α i of the field. Divider data α i are supplied to one of the first linear shift registers (A, to A4) and to the other first linear shift registers through α N1 , α N2 ,... multiplier circuits (51 to 53), respectively. Simultaneously, dividend data α i are supplied to one of the second linear shift registers (B, to B 4 ) and to the other second linear shift registers through α N1 , α N2 , ... multiplier circuits (58 to 60), respectively. "1" detector circuits (55 to 57) are connected to the outputs of the first linear shift registers (A, to A 4 ), respectively. The first linear shift registers (A, to A4) and the second linear shift registers (B 1 to B 4 ) are shifted several times until any "1" detector circuit (55 to 57) detects "1' in response to output signals from a 2-input AND gate (AND,,). When "1" is detected, a NOR gate (NOR, o ) supplies a signal of logical "0" to the AND gate (AND,,), whereby the AND gate (AND 11 ) stops supplying output signals. 2-input AND circuits (61 to 64) are connected at one input terminal to the outputs of the "1" detector circuits (54 to 57) and at the other input terminal to the outputs of the second linear shift registers (B, to B 4 ). The AND circuit connected to the "1" detector circuit supplies the data stored in the second linear shift register to which it is connected. The data representing the quotient of the division α i - a i , are delivered through an OR circuit (65).

公开(公告)号：EP0086659A3

公开(公告)日：1984-07-25

申请号：EP83300742

申请日：1983-02-15

Applicant: SONY CORPORATION

Inventor： Watanabe, Nobuhiko c/o Patent Division ,  Tanaka, Masato c/o Patent Division

IPC: G11B05/09 ,  G11B27/08 ,  G11B15/52

CPC classification number: G11B20/10527 ,  G11B15/52 ,  G11B19/28 ,  G11B20/1202 ,  G11B20/1204 ,  G11B20/18 ,  G11B27/032 ,  G11B27/10 ,  G11B2220/90 ,  G11B2220/913

Abstract: Apparatus for recording and reproducing a digital signal comprising successive data blocks, each data block including at least a plurality of data words and a block address which cycles with a predetermined phase relative to a reference signal and recorded on a recording medium (1) on which is also recorded a control signal in accordance with said reference signal, the apparatus comprising a head for reproducing the data words and block addresses within the data blocks from the recording medium (1), a time base corrector (15) for correcting a time base error contained in a reproduced data word, a head (HC) for reproducing the control signal from the recording medium (1), a counter (6) for generating a reference phase signal with a frequency of an integral multiple of more than twice the frequency of the control signal, a flip-flop circuit (5) for sampling the generated reference phase signal by the reproduced control signal so as to generate a phase compared output signal and a lock mode signal, and a servo loop (7 to 12) for controlling running of the recording medium (1) by the phase compared output signal.

公开(公告)号：EP0074644A3

公开(公告)日：1984-03-28

申请号：EP82108375

申请日：1982-09-10

Applicant: Hitachi, Ltd.

Inventor： Hoshino, Takashi ,  Arai, Takao ,  Nishimura, Keizo

IPC: G11B05/09 ,  G06F11/10 ,  H04L01/10

CPC classification number: G11B20/1809

Abstract: A PCM tape recording and reproducing apparatus for recording and reproducing an audio signal by using multi- track heads, comprises a frame interleaving device with a high dropout immunity function. The frame interleaving device comprises a distributor (10) for successively distributing continuous interleaved input data between tracks, within a multiplicity of tracks formed by splitting a magnetic tape, at a spacing of at least one track so that said continuous interleaved input data will not be shared between two continuous tracks in the same recording and reproducing direction, a data framing circuit (12) for forming a frame out of data to be distributed to each of said tracks and for applying said frame with a synchronization signal (2) at the top of said frame and with an error detection code (4) at the end of said frame, and a delay circuit (16, 20) for delaying data associated with a track by one frame or more with respect to data associated with a neighboring track in the same recording and reproducing as said track.

公开(公告)号：EP0083412A3

公开(公告)日：1983-11-09

申请号：EP82110817

申请日：1982-11-23

Applicant: International Business Machines Corporation

Inventor： Franaszek, Peter Anthony c/o IBM Corp.

IPC: G11B05/09

CPC classification number: G11B20/1426 ,  G06T9/005

Abstract: An algorithm and the hardware embodiment for producing a run lenght limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of one zero and a maximum of seven zeros between adjacent 1's. The code is generated by a sequential scheme that maps two bits of unconstrained data into three bits of constrained data. The encoder is a finite state machine whose internal state description requires three bits. The encoder requires a looka- head of one future input vector (two bits) and a look back at the last channel bit generated during the immediately preceding encoding operation. The error propagation due to a random error is, at most, four bits in bursts of five. The hardware implementation is extremely simple and can operate at very high data speeds.