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    Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions
    133.
    发明授权
    Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions 有权
    制造具有外延生长的应力诱导源极和漏极区域的MOS器件的方法

    公开(公告)号：US07670934B1

    公开(公告)日：2010-03-02

    申请号：US12359764

    申请日：2009-01-26

    Applicant: Rohit Pal ,  Frank Bin Yang

    Inventor： Rohit Pal ,  Frank Bin Yang

    IPC: H01L21/20 ,  H01L21/36

    CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84

    Abstract: Methods of fabricating a semiconductor device on and in a semiconductor substrate having a first region and a second region are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack overlying the first region and a second gate stack overlying the second region, etching into the substrate first recesses and second recesses, the first recesses aligned at least to the first gate stack in the first region, and the second recesses aligned at least to the second gate stack in the second region, epitaxially growing a first stress-inducing monocrystalline material in the first and second recesses, removing the first stress-inducing monocrystalline material from the first recesses, and epitaxially growing a second stress-inducing monocrystalline material in the first recesses, wherein the second stress-inducing monocrystalline material has a composition different from the first stress-inducing monocrystalline material.

    Abstract translation: 提供了在具有第一区域和第二区域的半导体衬底上和半导体衬底中制造半导体器件的方法。 根据本发明的示例性实施例，一种方法包括形成覆盖第一区域的第一栅极堆叠和覆盖第二区域的第二栅极堆叠，蚀刻到衬底中的第一凹陷和第二凹槽，第一凹陷至少对准 第一栅极堆叠在第一区域中，并且第二凹陷至少对准第二区域中的第二栅极堆叠，在第一和第二凹槽中外延生长第一应力诱导单晶材料，从第一和第二凹槽中去除第一应力诱导单晶材料 第一凹陷，并且在第一凹陷中外延生长第二应力诱导单晶材料，其中第二应力诱导单晶材料具有不同于第一应力诱导单晶材料的组成。

    TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD
    135.
    发明申请
    TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD 有权
    具有非对称嵌入式应变元件的晶体管器件及相关制造方法

    公开(公告)号：US20100012975A1

    公开(公告)日：2010-01-21

    申请号：US12176835

    申请日：2008-07-21

    Applicant: Rohit PAL ,  Frank Bin YANG ,  Michael J. HARGROVE

    Inventor： Rohit PAL ,  Frank Bin YANG ,  Michael J. HARGROVE

    IPC: H01L29/778 ,  H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

    Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

    Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

    Divider
    137.
    发明授权
    Divider 有权
    分隔线

    公开(公告)号：US07557621B2

    公开(公告)日：2009-07-07

    申请号：US11853819

    申请日：2007-09-12

    Applicant: Ting-Sheng Chao ,  Wei-Bin Yang ,  Yu-Lung Lo

    Inventor： Ting-Sheng Chao ,  Wei-Bin Yang ,  Yu-Lung Lo

    IPC: H03K23/00 ,  H03K21/00

    CPC classification number: H03K23/544 ,  H03K3/356156

    Abstract: A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.

    Abstract translation: 提供一个分频器。 分频器包括第一触发器，触发器阵列，第一NOT门，第二NOT门和电路。 第一个触发器可以由一个频率信号触发。 第一个非门耦合在最后一个第二触发器的正输出端和第一触发器之间。 第二NOT门耦合在最后一个第二触发器的正输出端和电路之间。 第一个非门和第二个非门由用于启用的模式控制信号控制。 如果N是奇数，则电路包括线，如果N是偶数，则电路包括第三NOT门。

    Multimerization of HIV-1 Vif protein as a therapeutic target
    138.
    发明授权
    Multimerization of HIV-1 Vif protein as a therapeutic target 有权
    HIV-1 Vif蛋白多聚化作为治疗靶点

    公开(公告)号：US07498138B2

    公开(公告)日：2009-03-03

    申请号：US11809953

    申请日：2007-06-04

    Applicant: Hui Zhang ,  Roger J. Pomerantz ,  Bin Yang

    Inventor： Hui Zhang ,  Roger J. Pomerantz ,  Bin Yang

    IPC: C12Q1/68

    CPC classification number: C07K14/005 ,  A61K38/00 ,  C12N2740/16322 ,  Y10S530/826

    Abstract: The HIV-1 protein Vif comprises a multimerization domain that allows Vif-Vif interaction and Vif multimerization, which is important for Vif function in the HIV-1 life-cycle. A method for screening for an antagonist of Vif comprises contacting the multimerization domain of Vif with a test compound that specifically binds the multimerization domain. Antagonists identified by the screening assay inhibit Vif multimerization. The antagonists inhibit essential functions of Vif and accordingly are useful as inhibitors of HIV-1 replication.

    Abstract translation: HIV-1蛋白Vif包含允许Vif-Vif相互作用和Vif多聚化的多聚化结构域，这对HIV-1生命周期中的Vif功能是重要的。 用于筛选Vif拮抗剂的方法包括使Vif的多聚化结构域与特异性结合多聚化结构域的测试化合物接触。 通过筛选测定鉴定的拮抗剂抑制Vif多聚化。 拮抗剂抑制Vif的基本功能，因此可用作HIV-1复制的抑制剂。

    Configuration Method and Engine for Inter-module Interfaces of Billing and Accounting
    139.
    发明申请
    Configuration Method and Engine for Inter-module Interfaces of Billing and Accounting 审中-公开
    计费和会计模块间接口的配置方法和引擎

    公开(公告)号：US20090024497A1

    公开(公告)日：2009-01-22

    申请号：US12115448

    申请日：2008-05-05

    Applicant: XIAOLE ZHANG ,  BIN YANG

    Inventor： XIAOLE ZHANG ,  BIN YANG

    IPC: G06Q40/00

    CPC classification number: G06Q40/00 ,  G06Q30/04

    Abstract: The present invention relates to a configuration method for inter-module interfaces of billing and accounting system, the steps are as follows: 1) interface configuration method is stored in the billing and accounting system by a form of static library named as libcdr.a, it is an invoking relationship between a configuration engine of the inter-module interfaces and each functional module class, that is each functional module of the billing and accounting system invoking the configuration engine to complete an unified conversion transaction of input and output format; 2) automatic analysis of each service data is configurable; all configuration information is integrated in one unified configuration file cdr.ini, two types of data information transaction are supported in this configuration file: one is network element raw input data, other is standardized data in the system.

    Abstract translation: 本发明涉及计费和计费系统的模块间接口的配置方法，其步骤如下：1）接口配置方法通过名为libcdr.a的静态库的形式存储在计费和计费系统中， 它是模块间接口的配置引擎和每个功能模块类之间的调用关系，即计费和计费系统的每个功能模块调用配置引擎，以完成输入和输出格式的统一转换事务; 2）每个服务数据的自动分析是可配置的; 所有配置信息集成在一个统一的配置文件cdr.ini中，此配置文件支持两种类型的数据信息事务：一种是网元原始输入数据，另一种是系统中的标准化数据。

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