公开(公告)号：EP1760866B1

公开(公告)日：2010-06-30

申请号：EP05024265.0

申请日：2005-11-08

Applicant: Fujitsu Microelectronics Limited

Inventor： Yoshino, Takahiro

IPC: H02M3/157 ,  H03M3/02

CPC classification number: H02M3/157 ,  H02M2001/0022 ,  H03M3/43 ,  H03M3/456 ,  H03M3/506

公开(公告)号：EP1677360B1

公开(公告)日：2010-05-12

申请号：EP05007947.4

申请日：2005-04-12

Applicant: Fujitsu Microelectronics Limited

Inventor： Shimamune, Yosuke ,  Katakami, Akira ,  Hatada, Akiyoshi ,  Shima, Masashi ,  Tamura, Naoyoshi

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/165 ,  H01L21/336 ,  H01L21/205 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  Y10S257/90

Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.

Abstract translation: 半导体器件包括：栅极电极，其通过栅极绝缘膜形成在硅衬底上，栅极绝缘膜对应于沟道区域，形成在硅衬底中的p型扩散区域的源极和漏极区域在侧壁绝缘膜的相应外侧 栅极电极和在硅衬底中在与硅衬底呈外延关系的侧壁绝缘膜的各外侧处形成的一对SiGe混合晶体区域，SiGe混合晶体区域由彼此相对的侧壁表面限定，其中 在每个SiGe混晶区域中，侧壁表面由相对于硅衬底的主表面形成相应不同角度的多个面形成。

公开(公告)号：EP1184981B1

公开(公告)日：2010-05-12

申请号：EP01302897.2

申请日：2001-03-28

Applicant: Fujitsu Microelectronics Limited

Inventor： Kanasugi, Masami, c/o Fujitsu Limited ,  Taniguchi, Shoji, c/o Fujitsu Limited ,  Kuroiwa, Koichi, c/o Fujitsu Limited ,  Hikita, Mahiro, c/o Fujitsu Limited

IPC: H03H17/06

CPC classification number: H03H17/0219 ,  H03H17/0294 ,  H03H17/0621

公开(公告)号：EP2037368A3

公开(公告)日：2010-04-28

申请号：EP08158811.3

申请日：2008-06-23

Applicant: Fujitsu Microelectronics Limited

Inventor： Tatsuoka, Masato FUJITSU LIMITED ,  Ike, Atsushi FUJITSU LIMITED

IPC: G06F11/36 ,  G06F11/34 ,  G06F9/46 ,  G06F17/50

CPC classification number: G06F11/3457 ,  G06F9/524 ,  G06F11/3632 ,  G06F11/3664

Abstract: A method of simulating software by use of a computer includes executing a program inclusive of a plurality of threads by a hardware model implemented as software on a software simulator, utilizing a monitor function of the simulator to collect information about accesses by monitoring accesses made by the plurality of threads with respect to resources provided in the hardware model, utilizing the monitor function to detect, from the collected information, overlapping accesses made to an identical resource area by two or more of the threads, and utilizing the monitor function to generate a message for warning of the overlapping accesses.

公开(公告)号：EP1746606B1

公开(公告)日：2010-03-31

申请号：EP06021810.4

申请日：2002-10-22

Applicant: Fujitsu Microelectronics Limited

Inventor： Fujioka, Shinya ,  Fujieda, Waichiro ,  Hara, Kota ,  Koga, Toru ,  Mori, Katsuhiro

IPC: G11C29/00

CPC classification number: G11C29/42 ,  G06F11/106 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C2211/4062

公开(公告)号：EP2149885A1

公开(公告)日：2010-02-03

申请号：EP09162648.1

申请日：2009-06-13

Applicant: Fujitsu Microelectronics Limited

Inventor： Hiraide, Takahisa

IPC: G11C29/14

CPC classification number: G11C29/14 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2029/0401

Abstract: An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal, and output of the memory corresponding to the changed address is latched in accordance with a latch signal having a cycle of an integral multiple of the first clock signal, data of the latch circuit is output via the input/output port in a cycle of the latch signal, an address of a memory cell corresponding to the output of the memory to be latched by the latch circuit is changed, and the latch and the output is repeated.

Abstract translation: 集成电路包括存储器; 用于测试存储器的存储器测试电路; 以及输入/输出端口，其中存储器测试电路包括输出存储器的输出的锁存电路，根据第一时钟信号改变要访问的存储器的地址，并且对应于改变的存储器的存储器的输出 地址按照具有第一时钟信号的整数倍的周期的锁存信号锁存，锁存电路的数据以锁存信号的周期经由输入/输出端口输出，存储单元的地址对应 到由锁存电路锁存的存储器的输出改变，并且锁存器和输出被重复。

公开(公告)号：EP1276139B1

公开(公告)日：2010-01-20

申请号：EP02252532.3

申请日：2002-04-09

Applicant: Fujitsu Microelectronics Limited

Inventor： Wang, Wensheng, c/o Fujitsu Limited ,  Fujiki, Mitsushi, c/o Fujitsu Limited ,  Nakamura, Ko, c/o Fujitsu Limited

IPC: H01L21/02

CPC classification number: H01L28/75 ,  H01L27/10814 ,  H01L28/55

公开(公告)号：EP1892725A3

公开(公告)日：2009-11-11

申请号：EP07114734.2

申请日：2007-08-22

Applicant: Fujitsu Microelectronics Limited

Inventor： Yamaguchi, Kota

IPC: G11C29/00 ,  G11C29/44

CPC classification number: G11C29/006 ,  G11C29/44 ,  G11C29/46 ,  G11C2029/4402

Abstract: A program circuit (1) activates a pass signal (PASZ) when a first program unit (FS) is programmed. The first program unit (FS) is programmed when a test of an internal circuit (4) is passed. A mode setting circuit (2) switches an operation mode to a normal operation mode or a test mode by external control. A state machine (3) allows a partial circuit (4a) of the internal circuit (4) to perform an unusual operation different from a normal operation when the pass signal (PASZ) is inactivated during the normal operation mode. By recognizing the unusual operation during the normal operation mode, it can be easily recognized that a semiconductor integrated circuit is bad. Since a failure can be recognized without shifting to the test mode, for example, a user who purchases the semiconductor integrated circuit can also easily recognize the failure.

公开(公告)号：EP1795903B1

公开(公告)日：2009-10-28

申请号：EP06003782.7

申请日：2006-02-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Shimizu, Katsuya ,  Sakima, Hiroyuki ,  Watai, Takahiro ,  Mizutani, Masaya ,  Aoki, Koju ,  Takekawa, Koji

IPC: G01P15/12 ,  G01P21/00 ,  G01L9/06 ,  G01L25/00 ,  G01L27/00

CPC classification number: G01P15/123 ,  G01L25/00 ,  G01P21/00 ,  G01R31/2829

公开(公告)号：EP1835506B1

公开(公告)日：2009-10-21

申请号：EP06115556.0

申请日：2006-06-15

Applicant: Fujitsu Microelectronics Limited

Inventor： Uchida, Toshiya c/o FUJITSU LIMITED

IPC: G11C7/22 ,  G11C8/12

CPC classification number: G11C11/406 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/408 ,  G11C11/4096