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    Control of frequency and/or phase characteristic in an (audio) amplifier
    133.
    发明公开
    Control of frequency and/or phase characteristic in an (audio) amplifier 失效
    einem（Audio）Verstärker的Steuerung von Frequenz- und / oder Phaseneigenschaften。

    公开(公告)号：EP0669712A1

    公开(公告)日：1995-08-30

    申请号：EP94830088.4

    申请日：1994-02-25

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Onetti, Andrea Mario ,  Tonella, Maurizio

    IPC: H03G5/02 ,  H03G1/00

    CPC classification number: H03G1/0088 ,  H03G5/025 ,  H03H11/1291

    Abstract: A circuit for controlling frequency and/or phase response characteristic of a signal amplification system or channel has a serial architecture composed of a plurality of cells and a selector for deriving the signal after any one of the cascaded cells. At least a component of the RC network of each cell is in the form of a plurality of modules of fractionary value connected in series. A short-circuiting switch is associated with each module of fractionary value and the overall effect may be selected by selecting the derivation node of the output signal and a certain configuration of the short-circuiting switches of the RC networks of the various cells. An outstanding flexibility of selection is achieved.

    Abstract translation: 用于控制信号放大系统或信道的频率和/或相位响应特性的电路具有由多个单元组成的串行架构和用于在任何一个级联单元之后导出信号的选择器。 每个小区的RC网络的至少一个组件是以串联连接的多个级数模块的形式。 短路开关与分数值的每个模块相关联，并且可以通过选择输出信号的导出节点和各种单元的RC网络的短路开关的特定配置来选择总体效果。 实现了出色的选择灵活性。

    Internal timing method and circuit for programmable memories
    134.
    发明公开
    Internal timing method and circuit for programmable memories 失效
    Interres Taktsteuerungsverfahren und Schaltungfürprogrammierbare Speichern。

    公开(公告)号：EP0668592A1

    公开(公告)日：1995-08-23

    申请号：EP94830070.2

    申请日：1994-02-18

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Pascucci, Luigi ,  Olivo, Marco ,  Golla, Carla Maria

    IPC: G11C16/06 ,  G11C7/00

    CPC classification number: G11C7/22 ,  G11C16/32

    Abstract: A circuit (1) generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit (1) includes a variable, asymmetrical propagation line (5, 37) composed of a succession of elementary delay elements (6-8, 38, 40) enabled or disabled on the basis of memorized logic signals (TIMS, PCS, DETS), the state of which is determined when debugging the memory (100) in which the circuit (1) is implemented.

    Abstract translation: 电路（1）产生灵活的时序，允许缓慢或快速的总体定时配置，以及通过提供两个（短或长）持续时间级别的预充电和检测间隔的两种配置。 为此，电路（1）包括可变的不对称传播线（5,37），其由基于存储的逻辑信号（TIMS）的一系列基本延迟元件（6-8,38,40）使能或禁用 ，PCS，DETS），当调试其中实现了电路（1）的存储器（100）时，确定其状态。

    Method for programming and testing a non-volatile memory
    135.
    发明公开
    Method for programming and testing a non-volatile memory 失效
    Verfahren zur Programmierung undPrüfungeinesnichtflüchtigenSpeichers。

    公开(公告)号：EP0665558A1

    公开(公告)日：1995-08-02

    申请号：EP94830032.2

    申请日：1994-01-31

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Olivo, Marco ,  Maccarrone, Marco

    IPC: G11C11/00 ,  G06F11/26 ,  G11C29/00

    CPC classification number: G11C29/46 ,  G11C29/14

    Abstract: A new method for testing an electrically programmable non-volatile memory and comprising a cell matrix and a state machine which governs the succession and timing of the memory programming phases by means of some control signals (WEN, CEN, OEN and DU) provides exclusion of the internal state machine and modification of the meaning of at least one of the control signals (WEN, CEN, OEN and DU) to program directly the cell matrix and then verify programming correctness.

    Abstract translation: 用于测试电可编程非易失性存储器并且包括通过一些控制信号（WEN，CEN，OEN和DU）来控制存储器编程阶段的连续和定时的单元矩阵和状态机的新方法提供了排除 内部状态机和至少一个控制信号（WEN，CEN，OEN和DU）的含义的修改，直接对单元矩阵进行编程，然后验证编程正确性。

    Interface TTL/CMOS circuit with temperature and supply voltage independent threshold level
    136.
    发明公开
    Interface TTL/CMOS circuit with temperature and supply voltage independent threshold level 失效
    TTL / CMOS-Schnittstellenschaltung mit von Temperatur und VersorgungspannungunabhängigemSchwellenpegel。

    公开(公告)号：EP0661812A1

    公开(公告)日：1995-07-05

    申请号：EP93830544.8

    申请日：1993-12-31

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Demicheli, Marco

    IPC: H03K19/003 ,  H03K19/0185

    CPC classification number: H03K19/018521 ,  H03K19/00384

    Abstract: A TTL/CMOS interface circuit having a tripping threshold unaffected by variations in temperature and supply voltage, comprises an input stage (Si), and an output stage (Su) which is an inverter.
    The input stage comprises a pair of inverters (M2,M3 and M5,M6) powered through a current mirror structure (M1,M4). The first of said inverters (M2,M3 and M5,M6) has an input terminal connected to a voltage reference (VREF) with the same value as the TTL switching threshold, and an output terminal connected to a control terminal (A) of the current mirror structure (M1,M4).
    The second inverter (M5,M6) has an input terminal (IN) forming the input terminal of the interface circuit and an output terminal connected to the output stage (Su).
    The interface circuit is supplied a voltage equal to the CMOS supply voltage.

    Abstract translation: 具有不受温度和电源电压变化影响的跳闸阈值的TTL / CMOS接口电路包括输入级（Si）和作为反相器的输出级（Su）。 输入级包括通过电流镜结构（M1，M4）供电的一对反相器（M2，M3和M5，M6）。 所述反相器（M2，M3和M5，M6）中的第一个具有连接到与TTL开关阈值相同值的电压基准（VREF）的输入端子，以及连接到控制端子（A）的输出端子 电流镜结构（M1，M4）。 第二反相器（M5，M6）具有形成接口电路的输入端的输入端（IN）和与输出级（Su）连接的输出端。 接口电路的电源电压等于CMOS电源电压。

    Circuit device and corresponding method for resetting non-volatile and electrically programmable memory devices
    137.
    发明公开
    Circuit device and corresponding method for resetting non-volatile and electrically programmable memory devices 失效
    电路和用于复位的非易失性的电可编程存储器装置相应的方法。

    公开(公告)号：EP0661714A1

    公开(公告)日：1995-07-05

    申请号：EP93830540.6

    申请日：1993-12-31

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Olivo, Marco ,  Padoan, Silvia

    IPC: G11C16/06

    CPC classification number: G11C16/30

    Abstract: A method for generating a reset signal in an electrically programmable non-volatile storage device (1) of a type which comprises a matrix (2) of memory cells and a control logic portion (3) being supplied a supply voltage (Vcc) and a programming voltage (Vpp), and a threshold detection circuit (5) adapted to detect a decrease in the supply voltage (Vcc), provides for the signal applied to the control logic (3) to be obtained as a change-over function between the output signal from the threshold detector (5) and a reset signal (POR) generated during the power-on transient of the device.

    Abstract translation: 一种用于在电可编程非易失性存储装置中产生的复位信号（1）类型，其包括存储单元的矩阵（2）和控制逻辑部（3）被供给的电源电压（Vcc）和方法 编程电压（VPP），以及阈值检测电路（5）angepasst以检测电源电压的降低（VCC）提供对施加到控制逻辑（3）的信号，以获得与之间的切换功能 电源接通该装置的瞬态期间产生从阈值检测器（5）和复位信号（POR）的输出信号。

    Redundancy circuitry for a semiconductor memory device
    138.
    发明公开
    Redundancy circuitry for a semiconductor memory device 失效
    Halbleiterspeicher mit redundancyanter Schaltung。

    公开(公告)号：EP0657814A1

    公开(公告)日：1995-06-14

    申请号：EP93830491.2

    申请日：1993-12-07

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Pascucci, Luigi ,  Golla, Carla Maria

    IPC: G06F11/20

    CPC classification number: G11C29/70

    Abstract: A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements, comprises a plurality of programmable non-volatile memory registers (1), which are programmable to store addresses of defective memory elements which must be replaced by redundancy memory elements; the redundancy circuitry comprises combinatorial circuit means (3) supplied by address signals (ADD) and supplying the non-volatile registers (1) with an inhibition signal (DIS) for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register (1).

    Abstract translation: 一种用于包括存储器元件矩阵的半导体存储器件的冗余电路，包括多个可编程非易失性存储器寄存器（1），其可编程以存储必须由冗余存储器元件代替的缺陷存储器元件的地址; 冗余电路包括由地址信号（ADD）提供并由非易失性寄存器（1）提供的组合电路装置（3），用于当矩阵的存储元件为 其地址与存储在非编程存储器寄存器（1）中的地址一致。

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