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    Flash EEPROM with integrated device for limiting the erase source voltage
    2.
    发明公开
    Flash EEPROM with integrated device for limiting the erase source voltage 失效
    闪存EEPROM系列产品Anordnung zur Begrenzung derLöschungder Source-Spannung

    公开(公告)号：EP0758129A1

    公开(公告)日：1997-02-12

    申请号：EP95830351.3

    申请日：1995-08-02

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Fratin, Lorenzo ,  Ravazzi, Leonardo ,  Riva, Carlo

    IPC: G11C16/06 ,  G11C5/14

    CPC classification number: G11C16/30 ,  G11C5/147

    Abstract: A Flash EEPROM comprises an array (1) of memory cells (MC) having a common source line (SL) connecting together source electrodes (S) of the memory cells (MC), said common source line (SL) being coupled to a positive potential (VPP) when the memory cells (MC) must be electrically erased, and resistive feedback means (R) coupled in series between said positive potential (VPP) and said common source line (SL). The Flash EEPROM comprises voltage limiting means (CL) coupled to said common source line (SL) for limiting the potential of the common source line (SL) to a prescribed maximum value (VCL) lower than said positive potential (VPP).

    Abstract translation: 闪存EEPROM包括具有连接存储单元（MC）的源电极（S）的公共源极线（SL）的存储单元（MC）的阵列（1），所述公共源极线（SL）耦合到正极 必须电擦除存储器单元（MC）的电位（VPP）和串联耦合在所述正电位（VPP）和所述公共源极线（SL）之间的电阻反馈装置（R）。 闪存EEPROM包括耦合到所述公共源极线（SL）的电压限制装置（CL），用于将公共源极线（SL）的电位限制到低于所述正电位（VPP）的规定的最大值（VCL）。

    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC
    3.
    发明公开
    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC 失效
    包含非易失性存储器单元和外围晶体管，和相应的类型的集成电路的电路的制造方法

    公开(公告)号：EP0751559A1

    公开(公告)日：1997-01-02

    申请号：EP95830281.2

    申请日：1995-06-30

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Clementi, Cesare ,  Ghidini, Gabriella ,  Riva, Carlo

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) having an intermediate dielectric multilayer including at least a lower dielectric material layer (8) and an upper silicon oxide layer (9) and the simultaneous provision in zones peripheral to the matrix of at least one first transistor type (2) having gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer (4) and a polycrystalline silicon layer (5) and the formation of the lower dielectric material layer (8), the process in accordance with the present invention calls for:

    removal of said layers from the peripheral zones (R2) of the matrix;
    deposition of said upper silicon oxide layer (9) over the memory cells (1),and over the substrate (3) in the areas (R2) of the peripheral transistors (2); and
    formation of a first silicon oxide layer (10) at least in the areas (R2) of the peripheral transistors (2).

    To provide additionally a second transistor type having gate dielectric of a second thickness, indicatively thinner than said first thickness, successive steps are added in accordance with the present invention.

    Abstract translation: 一种用于形成对集成电路工艺要求提供（1）在中间电介质多层具有包含非易失性存储器单元中的至少一个矩阵的至少一个下电介质材料层（8），并在上部氧化硅层（9） 和在区域周向具有第一厚度的栅极介电的至少一个第一晶体管类型（2）的基体中的同时提供。 与栅极氧化物层（4）和多晶硅层（5）和下电介质材料层的形成在形成浮置栅极之后（8），在雅舞蹈过程与本发明要求：去除所述层的 从基体的外周区域（R2）; 说，在存储单元（1）上的氧化硅层（9）的沉积，并用在外围晶体管（2）的区域（R2）的基板（3）; 和形成在外围晶体管（2）的区域（R2）的至少一个第一氧化硅层（10）的。 以提供另外具有第二厚度的栅极介电的第二晶体管的类型，指示性比所述第一厚度薄，在雅舞蹈添加与本发明的连续步骤。

    EPROM and Flash-EEPROM non-volatile memory and method of manufacturing the same
    4.
    发明公开
    EPROM and Flash-EEPROM non-volatile memory and method of manufacturing the same 失效
    非易失性EPROM和闪存EEPROM内存和进程及其制备

    公开(公告)号：EP0696050A1

    公开(公告)日：1996-02-07

    申请号：EP94830363.1

    申请日：1994-07-18

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Fratin, Lorenzo ,  Ravazzi, Leonardo ,  Riva, Carlo

    IPC: H01L21/00 ,  H01L21/336 ,  H01L29/10 ,  H01L29/788

    CPC classification number: H01L29/66825 ,  H01L29/1045 ,  H01L29/7881

    Abstract: A nonvolatile memory (40) having a cell (31) comprising an N⁺ type source region (24) and drain region (12) embedded in a P⁻ type substrate (4) and surrounded by respective P-pockets (26, 16). The drain and source P-pockets (16, 26) are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell (31) also presents a higher breakdown voltage as compared with known cells.

    Abstract translation: 嵌入在P A的非易失性存储器（40），具有包含N的细胞（31）<+>型源区（24）和漏区（12）< - >型衬底（4）和由respectivement P-凹槽围绕着（ 26，16）。 漏极和源极P-口袋（16，26）形成在设计用于优化的注入能量和剂量为确保电池的可扩展性和避免跳回电压的损害两个不同的高角度硼注入步骤。 因此所得到的细胞（31）呈现出更高的击穿电压与已知的细胞相比。

    Double polysilicon EEPROM cell and corresponding programming method
    6.
    发明公开
    Double polysilicon EEPROM cell and corresponding programming method 失效
    EEPROM-Zelle mit Doppelter Polysiliziumschicht undzugehörigesProgrammierungsverfahren。

    公开(公告)号：EP0612107A1

    公开(公告)日：1994-08-24

    申请号：EP93830061.3

    申请日：1993-02-19

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Pio, Federico ,  Riva, Carlo

    IPC: H01L27/115 ,  H01L29/788 ,  G11C16/04

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

    Abstract: A method for programming a two-level polysilicon EEPROM memory cell, which cell is implemented in MOS technology on a semiconductor substrate (2) and comprises a floating gate (12) transistor and a further control gate (15) overlying the floating gate (12) with a dielectric layer (11) therebetween, provides for the application of a negative voltage to the control gate (15) during the cell (1) write phase. This enables the voltages being applied across the thin tunnel oxide layer to be distributed so as to reduce the maximum amount of energy of the "holes" and improve the oxide reliability. In addition, by controlling the rise speed of the impulse to the drain region during the write phase, and of the impulse to the control gate during the erase phase, the maximum current flowing through the tunnel oxide can be set and the electric field being applied to the tunnel oxide kept constant, thereby the device life span can be extended.

    Abstract translation: 一种用于编程两级多晶硅EEPROM存储单元的方法，该单元在半导体衬底（2）上的MOS技术中实现，并且包括浮置栅极（12）晶体管和覆盖浮置栅极（12）的另外的控制栅极（15） ），其间具有介电层（11），用于在单元（1）写入阶段期间向控制栅极（15）施加负电压。 这使得施加在薄隧道氧化物层上的电压被分布，以便减少“空穴”的最大能量并提高氧化物的可靠性。 此外，通过在写入阶段期间控制到漏极区域的脉冲的上升速度以及在擦除阶段期间对控制栅极的脉冲的上升速度，可以设定流过隧道氧化物的最大电流并施加电场 隧道氧化物保持恒定，从而可延长设备使用寿命。

    Process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide by using differential oxidation
    7.
    发明公开
    Process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide by using differential oxidation 失效
    通过使用差异氧化制造单层多晶硅和氧化亚锡的EEPROM存储单元的工艺

    公开(公告)号：EP0416687A3

    公开(公告)日：1991-10-02

    申请号：EP90202302.7

    申请日：1990-08-28

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Ghezzi, Paolo ,  Riva, Carlo ,  Valentini, Grazia

    IPC: H01L21/336 ,  H01L29/788

    CPC classification number: H01L27/11517 ,  H01L21/28167 ,  H01L21/28211 ,  H01L21/31662 ,  H01L27/115 ,  H01L29/7883

    Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10′) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10˝, 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.

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