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131.发明授权公开(公告)号：US09992916B2
公开(公告)日：2018-06-05
申请号：US14595391
申请日：2015-01-13
Inventor： Giovanni Luca Torrisi , Domenico Massimo Porto , Sergio Lecce , Manuel Gaertner
CPC classification number: H05K7/20945 , H01L23/34 , H01L2924/0002 , H03K2017/0806 , Y10T307/773 , H01L2924/00
Abstract: A thermal control process for an electronic power device including a multi-junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.
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公开(公告)号：US09606611B2
公开(公告)日：2017-03-28
申请号：US14591779
申请日：2015-01-07
Applicant: STMicroelectronics Application GmbH
Inventor： Fred Rennig
IPC: G06F1/26 , G06F1/32 , H04L12/403
CPC classification number: G06F1/3243 , G06F1/3209 , G06F1/3234 , G06F1/3287 , G06F1/3293 , H04L12/403 , Y02D10/10
Abstract: A bus microcontroller includes a processor circuit having at least one unit designed for performing one or more functions due to a bus command via a communication bus, a power control circuit adapted to be coupled to a transmitter-receiver circuit for receiving bus messages via the communication bus, and a means for placing at least part of the processor circuit into a reduced-power operating mode without placing the entire processor circuit into the reduced-power operating mode. The power control circuit is designed to evaluate incoming bus messages with respect to an activation bus message containing information on activating at least part of the processor circuit, and to output a corresponding activation control signal. The bus microcontroller also includes means for activating at least a part of the processor circuit that is placed in a reduced-power operating mode, in response to output of an activation control signal of the power control circuit.
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133.发明申请公开(公告)号：US20130214724A1
公开(公告)日：2013-08-22
申请号：US13849374
申请日：2013-03-22
Applicant: STMicroelectronics Application GmbH
Inventor： Reiner Schwartz
IPC: H02J7/00
CPC classification number: H02J7/0019 , B60L11/1866 , B60L2240/547 , B60L2240/549 , H02J7/0016 , Y02T10/7005 , Y02T10/7061
Abstract: A method and an active battery balancing circuit for balancing an electric charge in a plurality of cells of a battery that are electrically connected in series is disclosed. A first subset of the cells of the battery is electrically connected to an inductance for providing a current flow from the first subset through the inductance. The first subset of the cells is disconnected from the inductance, and a current is allowed to flow from the inductance into a second subset of the cells of the battery. At least one of the first and the second subset of the cells of the battery comprises two or more cells.
Abstract translation: 公开了一种用于平衡串联电连接的电池的多个单电池中的电荷的方法和有源电池平衡电路。 电池的单元的第一子集电连接到电感，以提供来自第一子集的电流流过电感。 电池的第一子集与电感断开，并且允许电流从电感流入电池单元的第二子集。 电池单元的第一和第二子集中的至少一个包括两个或更多个单元。
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公开(公告)号：US12259844B2
公开(公告)日：2025-03-25
申请号：US17829902
申请日：2022-06-01
Inventor： Giuseppe Cavallaro , Fred Rennig
IPC: G06F13/42 , G05B19/042 , G06F11/10 , G06F13/38 , G06F13/40
Abstract: In an embodiment a microcontroller includes a processing unit and a deserial-serial peripheral interface (DSPI) module, wherein the deserial-serial peripheral interface module is coupleable to a communication bus configured to operate according to a selected communication protocol, wherein the processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol, calculate, as a function of the user data, a cyclic redundancy check (CRC) value intended for inclusion in the outgoing frame, compose the outgoing frame by including the user data and the calculated CRC value into the outgoing frame, produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame and program a data register of the deserial-serial peripheral interface module with the DSPI frame, and wherein the deserial-serial peripheral interface module is configured to transmit the DSPI frame via the communication bus.
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公开(公告)号：US12210609B2
公开(公告)日：2025-01-28
申请号：US17515149
申请日：2021-10-29
Inventor： Avneep Kumar Goyal , Thomas Szurmant
Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.
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Patent Agency Ranking
公开(公告)号：US12147209B2
公开(公告)日：2024-11-19
申请号：US17704675
申请日：2022-03-25
Inventor： Rosario Martorana , Mose' Alessandro Pernice , Roberto Colombo
IPC: G05B19/042
Abstract: A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.
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137.发明公开公开(公告)号：US20240362176A1
公开(公告)日：2024-10-31
申请号：US18764940
申请日：2024-07-05
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G05B19/042 , G06F9/54 , G06F11/07 , G06F11/10 , G06F13/40 , G06F13/42 , H03M13/09 , H04L12/40 , H04L12/403
CPC classification number: G06F13/362 , G05B19/042 , G06F9/542 , G06F11/0739 , G06F11/0757 , G06F11/0772 , G06F11/1004 , G06F13/4068 , G06F13/4282 , H04L12/40006 , H04L12/40013 , H04L12/40078 , H04L12/403 , G05B2219/1215 , G05B2219/2231 , G05B2219/31179 , H03M13/09 , H04L2012/40215
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US12118376B2
公开(公告)日：2024-10-15
申请号：US17235206
申请日：2021-04-20
Inventor： Deepak Baranwal , Amritanshu Anand , Roberto Colombo , Boris Vittorelli
CPC classification number: G06F9/45558 , G06F9/455 , G06F9/45533 , G06F9/48 , G06F9/4812 , G06F9/4843 , G06F9/485 , G06F9/4856 , G06F9/4881 , G06F9/50 , G06F9/5083 , G06F9/5088 , G06F2009/4557 , G06F2009/45575
Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.
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公开(公告)号：US12068057B2
公开(公告)日：2024-08-20
申请号：US18056803
申请日：2022-11-18
Applicant: STMicroelectronics S.r.l. , STMicroelectronics International N.V. , STMicroelectronics Application GMBH
Inventor： Asif Rashid Zargar , Nicolas Bernard Grossier , Charul Jain , Roberto Colombo
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1069
Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.
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公开(公告)号：US12068048B2
公开(公告)日：2024-08-20
申请号：US17815807
申请日：2022-07-28
Inventor： Vivek Mohan Sharma , Roberto Colombo
CPC classification number: G11C29/42 , G11C29/36 , G11C29/48 , G11C2029/3602
Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
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