公开(公告)号：NO980511A

公开(公告)日：1998-02-11

申请号：NO980511

申请日：1998-02-06

Applicant: SYMBIOS LOGIC INC

Inventor： DULAC KEITH BERNARD ,  FREEMAN PAUL MICHAEL

IPC: H04N5/93 ,  H04N7/173 ,  H04N21/472

CPC classification number: H04N21/47202 ,  H04N7/17318

公开(公告)号：AU3267797A

公开(公告)日：1998-01-21

申请号：AU3267797

申请日：1997-06-25

Applicant: SYMBIOS LOGIC INC

Inventor： ALLMAN DERRYL D J ,  GREGORY JOHN W ,  YAKURA JAMES P ,  KWONG DIM LEE

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/423 ,  H01L29/92 ,  H01L21/3205

公开(公告)号：AU3100997A

公开(公告)日：1998-01-21

申请号：AU3100997

申请日：1997-06-16

Applicant: SYMBIOS LOGIC INC

Inventor： SCHULTZ RICHARD T

IPC: H03K3/037

Abstract: A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal. The method preferably includes the step of generating an output signal in response to the second data input signal and the second clock signal, the output signal having a reduced metastable effect.

公开(公告)号：DE69223267D1

公开(公告)日：1998-01-08

申请号：DE69223267

申请日：1992-03-12

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： JIBBE MAHMOUD K ,  MCCOMBS CRAIG C

IPC: G06F3/00 ,  G06F11/07 ,  G06F13/00 ,  G06F13/36 ,  G06F3/06 ,  G06F11/00 ,  G06F13/40

公开(公告)号：AU3103197A

公开(公告)日：1998-01-07

申请号：AU3103197

申请日：1997-06-18

Applicant: SYMBIOS LOGIC INC

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/16 ,  G06F11/267 ,  G06F12/16 ,  G11B20/18

Abstract: A distributed XOR device that preferably includes a data buffer. The data buffer preferably stores at least two data blocks in an interleaved manner. The data blocks contain data words, and a specific data word for each data block contains CRC bits. In response to certain addresses, the data words of the data blocks are output from the data buffer in an interleaved manner. An XOR engine circuit receives the interleaved data words. The XOR engine circuit preferably includes a data XOR circuit and an error detection circuit. The data XOR circuit preferably performs an exclusive-OR function on pairs of data words, where one data word is from a one data block and the other data word in from the other data block. The generated combinations or results are output to the error detection circuit. The error detection circuit generates CRC bits from the generated combinations or results. Preferably, the CRC bits are encoded with a constant IDCRC. These encoded CRC bits are compared to the result of the exclusive-OR function on the CRC bits of the data blocks. If these bits are not equal, an error signal is output. The comparison therefore checks whether the XOR engine circuit or the data blocks are in error.

公开(公告)号：DE69031603D1

公开(公告)日：1997-11-27

申请号：DE69031603

申请日：1990-01-16

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： CRAFTS HAROLD S

IPC: H01L27/092 ,  H01L21/82 ,  H01L21/8238 ,  H01L27/118

公开(公告)号：DE69031489D1

公开(公告)日：1997-10-30

申请号：DE69031489

申请日：1990-12-20

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： LANGFORD THOMAS L ,  BULLINGER PHILIP W ,  FARRIS RICHARD D

IPC: G01R31/02 ,  H01L21/66 ,  H01L27/02

Abstract: An integrated circuit includes a monitor device connected between a pin for connection to the more positive lead of the power supply or the less positive lead of the power supply and the more positive voltage supply conductors or the less positive voltage supply conductors on the integrated circuit substrate. The monitor circuit has a threshold circuit (112) such that, insignificant perturbations will not trigger the monitor. The monitor circuit includes a comparator (120) having a reference voltage input (122) such that the same circuit may be used for the more positive side of the power supply, as well as, the less positive side with straightforward modifications. When the monitor circuit detects a significant fault, i.e. one that could falsely switch part of the integrated circuit, it sets a flip-flop (141) to record such an occurrence. The monitor flip-flop (141) cannot be reset by the usual reset signals, in order to prevent it from being cleared by normal diagnostics and error recovery operations.

公开(公告)号：AU2513797A

公开(公告)日：1997-10-22

申请号：AU2513797

申请日：1997-03-26

Applicant: SYMBIOS LOGIC INC

Inventor： JANDER MARK J

IPC: G06F5/06

Abstract: A first-in-first-out (FIFO) memory system. The FIFO memory system contains a first fall-through FIFO having an input and an output. A pointer-based FIFO having an input and an output, wherein the input of the pointer-based FIFO is connected to the output of the first fall-through FIFO. The FIFO memory system also includes a second fall-through FIFO having an input and an output, wherein the input of the second fall-through FIFO is connected to the output of the pointer-based FIFO, wherein data placed into the input of the first fall-through FIFO appears at the output of the second fall-through FIFO in a first-in-first-out basis.

公开(公告)号：DE69220134D1

公开(公告)日：1997-07-10

申请号：DE69220134

申请日：1992-03-11

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： JIBBE MAHMOUD K ,  MCCOMBS CRAIG C

IPC: G06F3/06 ,  G06F9/48 ,  G06F13/24

Abstract: A system interrupt signal for a disk array is generated by selectively combining interrupt signals received from individual disk drives and other interrupt signal sources within the disk array. The circuit for generating the system interrupt signal includes a first logic circuit (140) for combining a first group of selected interrupt signals to generate a group interrupt signal having an active state when each one of the signals in the first group is at an active state, and a second logic circuit (120) which combines a second group of selected interrupt signals to generate an independent interrupt signal having an active state when any one of the interrupt signals of the second group has an active state. The group and independent interrupt signals are gated together to generate a common system interrupt signal. The first and second logic circuits (120,140) can be reconfigured to combine, pass or ignore interrupt signals as selected by the system user. The circuit includes filtering and latching circuits (160,170) to prevent interference with an existing array interrupt signal during reconfiguration of the group or independent interrupt logic circuits (120,140).

公开(公告)号：NO972209D0

公开(公告)日：1997-05-14

申请号：NO972209

申请日：1997-05-14

Applicant: SYMBIOS LOGIC INC

Inventor： PRATER JAMES S ,  CHRISTIAN KEVIN G

IPC: G11B20/10 ,  H04L25/03

Abstract: The invention provides for signal processing apparatus (100) having a first filter means (102) for adjusting an input signal based on past data output from the apparatus (130), a summing means (106) is arranged to sum signals from the first filter means (102) and from a second filter means (104) to produce a sum signal. The apparatus also includes a symbol detection means (108) for generating an output signal from the sum signal and the second filter means (104) is arranged to provide adjustments in the output signal based on the peaks and polarity of past signals generated by the symbol detection means (108). A control means can be included for controlling the filtering properties of both the first and second filter means, wherein the control means controls the filtering properties based on the past output signals from the symbol detection means.