公开(公告)号：WO0124171A9

公开(公告)日：2002-09-26

申请号：PCT/US0026851

申请日：2000-09-29

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： WONG BUNSEN Y

IPC: G11B5/73 ,  G11B5/84 ,  G11B5/70 ,  B05D5/12 ,  G11B5/72

CPC classification number: G11B5/7325 ,  G11B5/8404

Abstract: An underlayer (8A) of a magnetic recording medium (16) includes first and second non-magnetic, chromium-based layers (18, 20), at least one of the first and second chromium-based layers being a chromium alloy. The lattice parameter of the composite underlayer is between the lattice parameters of the first and second chromium-based layers. Recognizing this permits one to predictably adjust the lattice parameter of the composite underlayer to be close to the lattice parameter of the magnetic layer (10) so to optimize magnetic and parametric properties.

Abstract translation: 磁记录介质（16）的底层（8A）包括第一和第二非磁性铬基层（18,20），第一和第二铬基层中的至少一个是铬合金。 复合底层的晶格参数在第一和第二铬基层的晶格参数之间。 认识到这允许可预测地将复合底层的晶格参数调整为接近磁性层（10）的晶格参数，从而优化磁性和参数特性。

公开(公告)号：WO9835344A2

公开(公告)日：1998-08-13

申请号：PCT/US9802740

申请日：1998-02-11

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： LEE JONG SEUK

IPC: G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11B

CPC classification number: H01L27/11519 ,  G11C16/0416 ,  G11C16/08

Abstract: The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled. A sector of the nonvolatile Flash EEPROM array preferably comprises 8 rows and 512 columns of transistors and a block preferably comprises 128 vertically stacked sectors.

Abstract translation: 本发明提供了一种新颖的非易失性闪存EEPROM阵列设计，其允许阵列，块或扇区擦除功能。 本发明的相对简单的晶体管设计布局允许擦除EEPROM阵列的小部分而不影响存储在阵列的剩余部分中的数据。 另外，考虑到闪存EEPROM阵列的块结构布局，阵列中的相邻块可以共享晶体管控制电路，从而使阵列的尺寸最小化。 新颖的非易失性闪存EEPROM阵列优选地包括多个块，其包括多个NOR栅极晶体管的扇区。 每个晶体管都有漏极，源极和控制栅极。 优选地，列中每个晶体管的漏极电耦合，一行中的每个晶体管的控制栅极电耦合，并且扇区中的所有晶体管的源电耦合。 非易失性闪存EEPROM阵列的扇区优选地包括8行和512列的晶体管，并且块优选地包括128个垂直堆叠的扇区。

公开(公告)号：WO1995005633A2

公开(公告)日：1995-02-23

申请号：PCT/US1994008601

申请日：1994-08-01

Applicant: HYUNDAI ELECTRONICS AMERICA, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  RARICK, Leonard, Dennis

IPC: G06F07/50

CPC classification number: G06F7/5318 ,  G06F7/49947 ,  G06F7/508

Abstract: A carry-look-ahead adder for adding an addend and an augend and generating a final sum. The addend, augend, and final sum are binary numbers, each having a plurality of bits. Bits of the same order in the addend and the augend are organized into columns. The adder has at least one data reduction stage, each data reduction stage having at least one multi-column full adder. The data reduction stages use the columns of addend and augend bits to generate a reduced addend and a reduced augend, with the reduced augend having fewer bits than the augend. A generate/propagate calculation stage then uses the reduced addend and the reduced augend for calculating generate and propagate data, the generate/propagate calculation stage having been modified to account for the reduction of the addend and augend. A carry-generate stage then uses the generate and propagate data to generate at least one final carry. Finally, a final sum calculation stage uses the reduced addend, the reduced augend, and the final carries for calculating the final sum. The data reduction stages reduce the inputs to the generate/propagate calculation stage thereby reducing the number of inputs to the carry-generate circuit. With fewer inputs, the number of stages in the carry-generate circuit can be reduced, thus resulting in a faster implementation of the carry-look-ahead adder.

Abstract translation: 用于添加加数和加法并产生最终和的进位前瞻加法器。 加法，加法和最后的和是二进制数，每个都有多个位。 加数和加法中相同顺序的位被组织成列。 加法器具有至少一个数据缩减级，每个数据缩减级具有至少一个多列全加器。 数据缩减阶段使用加数和加数位列来生成减少的加数和减小的加法，减少的加法比具有比加法器少的位。 生成/传播计算阶段然后使用减少的加数和减小的加法来计算生成和传播数据，生成/传播计算阶段已被修改以减少加数和加减。 进位生成阶段然后使用生成和传播数据来生成至少一个最终进位。 最后，最终计算阶段使用减少的加数，减少的加法，以及计算最终总和的最终计算阶段。 数据减少级将输入减少到生成/传播计算级，从而减少进位产生电路的输入数。 通过较少的输入，可以减少进位产生电路中的级数，从而导致进位前进加法器的更快实现。

公开(公告)号：WO0026941A9

公开(公告)日：2000-09-28

申请号：PCT/US9923694

申请日：1999-10-12

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： OH JONG-HOON

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  H01L

CPC classification number: G11C8/14 ,  G11C8/08 ,  G11C11/4085

Abstract: A hierarchical word line driving structure uses a shared inverter circuit architecture which allows for lower power consumption and a pulsed control signal to ensure accurate memory retrieval. The shared inverter word line structure includes a row decoder, a first sub-word line driver, a second sub-word line driver, and an interconnect line. The first sub-word line driver includes an inverting circuit for inverting the signal propagating along the global word line, while the second sub-word line driver does not. The interconnect line is coupled between the first and second sub-word line drivers to communicate the inverted signal therebetween. A pulsed control signal is supplied to clamping transistors connected to unselected word lines to ensure they remain clamped to ground.

公开(公告)号：WO9828869A3

公开(公告)日：1998-10-15

申请号：PCT/US9723384

申请日：1997-12-19

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： RAO PADMANABHA R

IPC: H04B7/185 ,  H04H40/90 ,  H04N7/173 ,  H04H

CPC classification number: H04H40/90 ,  H04B7/18523 ,  H04N7/17318 ,  H04N21/25883 ,  H04N21/25891 ,  H04N21/2668 ,  H04N21/4383 ,  H04N21/44222 ,  H04N21/4755 ,  H04N21/6543 ,  H04N21/6582 ,  H04N21/812

Abstract: A method and apparatus are disclosed for providing data (200) over data broadcasting systems to specially targeted audiences (202, 204). In accordance with the invention, user classifications may be obtained for a plurality of data users. The classifications for a predetermined data content may also be obtained. Once the user and programming content classifications are obtained, the predetermined data content, the regular content, and a mapping means are transmitted to multiple user reception units over separate transmission services. The mapping means indicates when the individual reception units are to switch automatically to the predetermined data content from the regular data content (210, 212, 214, 216), and may be configured in accordance with the user classifications and the predetermined data content so that each user obtains and is presented with the predetermined programming content that substantially matches the user's classifications.

公开(公告)号：WO1998028869A2

公开(公告)日：1998-07-02

申请号：PCT/US1997023384

申请日：1997-12-19

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： HYUNDAI ELECTRONICS AMERICA ,  RAO, Padmanabha, R.

IPC: H04H00/00

CPC classification number: H04H40/90 ,  H04B7/18523 ,  H04N7/17318 ,  H04N21/25883 ,  H04N21/25891 ,  H04N21/2668 ,  H04N21/4383 ,  H04N21/44222 ,  H04N21/4755 ,  H04N21/6543 ,  H04N21/6582 ,  H04N21/812

Abstract: A method and apparatus are disclosed for providing data over data broadcasting systems to specially targeted audiences. In accordance with the invention, user classifications may be obtained for a plurality of data users. The classifications for a predetermined data content may also be obtained. Once the user and programming content classifications are obtained, the predetermined data content, the regular data content, and a mapping means are transmitted to multiple user reception units over separate transmission services. The mapping means indicates when the individual reception units are to switch automatically to the predetermined data content from the regular data content, and may be configured in accordance with the user classifications and the predetermined data content classifications so that each user obtains and is presented with the predetermined programming content that substantially matches that user's classifications.

Abstract translation: 公开了一种用于将数据广播系统的数据提供给特定目标的观众的方法和装置。 根据本发明，可以为多个数据用户获得用户分类。 也可以获得预定数据内容的分类。 一旦获得用户和节目内容分类，预定数据内容，常规数据内容和映射装置通过单独的传输服务被发送到多个用户接收单元。 映射装置指示各个接收单元何时将从常规数据内容自动切换到预定数据内容，并且可以根据用户分类和预定数据内容分类来配置，使得每个用户获得并呈现 基本匹配该用户分类的预定节目内容。

公开(公告)号：WO0003507A3

公开(公告)日：2001-06-14

申请号：PCT/US9915365

申请日：1999-07-08

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： KANG INCHUL ,  LAUDEL KENNAN

IPC: H03L7/08 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/7085 ,  H04B1/709 ,  H04J11/00 ,  H04J13/00 ,  H04B15/00 ,  H04K1/00 ,  H04L27/30

CPC classification number: H04B1/7085 ,  H04B1/70757 ,  H04B1/7077 ,  H04B1/709 ,  H04B2201/70707 ,  H04J13/0022

Abstract: A variable rate correlation circuit (fig.3) for conserving power includes a variable clock source (340), a local PN source (360), and a correlator (320). The local PN source (360) further includes a local generator (361) and a resampler (364). The variable clock source (340) provides a normal clock rate and a lower clock rate. The local generator (361) supplies the local PN sequence at the normal clock rate. The resampler (364) receives the local PN sequence sampled at the normal clock rate and output the local PN sequence sampled at the lower clock rate. The correlator (320) receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a correlated result.

Abstract translation: 用于节省功率的可变速率相关电路（图3）包括可变时钟源（340），本地PN源（360）和相关器（320）。 本地PN源（360）还包括本地发生器（361）和重采样器（364）。 可变时钟源（340）提供正常的时钟速率和较低的时钟速率。 本地发生器（361）以正常时钟速率提供本地PN序列。 重采样器（364）接收以正常时钟速率采样的本地PN序列，并输出以较低时钟速率采样的本地PN序列。 相关器（320）接收较低采样的本地PN序列，接收的PN序列和较低时钟速率信号，使接收到的本地PN序列以较低的时钟速率相关，以产生相关结果。

公开(公告)号：WO1998021878A2

公开(公告)日：1998-05-22

申请号：PCT/US1997020996

申请日：1997-11-14

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： HYUNDAI ELECTRONICS AMERICA ,  BEDARD, Karen

IPC: H04N00/00

CPC classification number: H04N21/482 ,  H04N5/44543

Abstract: A method and apparatus are disclosed for locating desired television programs and categories of television programs. To facilitate viewer access to preferred programming, program guide information of an electronic program guide may be searched in accordance with viewer-specified or system default parameters. Viewer-specified parameters illustratively include program names, partial program names, categories of programming, and subcategories of programming. Once the search is complete, a means is provided for displaying information on television programs in the categories, or with titles, that match the television program titles or categories of interest.

Abstract translation: 公开了一种用于定位所需电视节目和电视节目类别的方法和装置。 为了便于观看者访问优选节目，可以根据观众指定的或系统的默认参数搜索电子节目指南的节目指南信息。 查看器指定的参数说明性地包括程序名称，部分程序名称，编程类别和编程子类别。 搜索完成后，提供一种用于显示与电视节目标题或兴趣类别相匹配的类别或标题中的电视节目的信息的方法。

公开(公告)号：WO1996017295A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015043

申请日：1995-11-20

Applicant: HYUNDAI ELECTRONICS AMERICA, INC. ,  METAFLOW TECHNOLOGIES, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  METAFLOW TECHNOLOGIES, INC. ,  ISAMAN, David, L.

IPC: G06F09/40

CPC classification number: G06F9/3844

Abstract: A branch prediction technique which increases the likelihood of correctly predicting the direction of a conditional branch instruction is presented. The technique is based on the observation that many branches have run lengths that are constant or slowly-varying, i.e. several consecutive runs of 1's are of the same length. The technique uses the history stored for each branch, which history is enhanced by two small counters (102, 113), an up counter (102) and a down counter (113). These counters (102, 113) operate in conjunction with a state machine branch predictor (101) of the prior art for very accurate predictions.

Abstract translation: 提出了一种提高正确预测条件转移指令方向的可能性的分支预测技术。 该技术基于观察，许多分支的运行长度是恒定的或缓慢变化的，即1的连续运行的长度是相同的。 该技术使用为每个分支存储的历史，该历史由两个小计数器（102,113），向上计数器（102）和向下计数器（113）增强。 这些计数器（102,113）与现有技术的状态机分支预测器（101）一起工作，用于非常准确的预测。

公开(公告)号：WO9505633A3

公开(公告)日：1995-03-23

申请号：PCT/US9408601

申请日：1994-08-01

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： RARICK LEONARD DENNIS

IPC: G06F7/483 ,  G06F7/50 ,  G06F7/508 ,  G06F7/52

CPC classification number: G06F7/5318 ,  G06F7/49947 ,  G06F7/508

Abstract: A carry-look-ahead adder (30) for adding an addend (4) and an augend (6) and generating a final sum (8). The addend, augend, and final sum are binary numbers, each having a plurality of bits. Bits of the same order in the addend and the augend are organized into columns. The adder has at least one data reduction stage, each data reduction stage having at least one multi-column full adder. The data reduction stages use the columns of addend and augend bits to generate a reduced addend (38) and a reduced augend (40), with the reduced augend having fewer bits than the augend. A generate/propagate calculation stage (34) then uses the reduced addend and the reduced augend for calculating generate (42) and propagate data (44), the generate/propagate calculation stage having been modified to account for the reduction of the addend and augend. A carry-generate stage (36) then uses the generate and propagate data to generate at least one final carry (48). Finally, a final sum calculation stage uses the reduced addend, the reduced augend, and the final carries for calculating the final sum. The data reduction stages reduce the inputs to the generate/propagate calculation stage thereby reducing the number of inputs to the carry-generate circuit. With fewer inputs, the number of stages in the carry-generate circuit can be reduced, thus resulting in a faster implementation of the carry-look-ahead adder.