公开(公告)号：KR1020050063620A

公开(公告)日：2005-06-28

申请号：KR1020030095039

申请日：2003-12-22

Applicant: 한국전자통신연구원

Inventor： 임인기 ,  김일규 ,  박형일 ,  방승찬 ,  정희범

IPC: H04B7/155

CPC classification number: H04W88/08 ,  H04B7/0491 ,  H04B7/0617 ,  H04W16/28

Abstract: 본 발명은 스마트 안테나 기지국 변조 장치에 관한 것이다. 스마트 안테나 기지국 시스템은 기존 기지국 시스템에 비하여 많은 가입자를 수용 및 통신 품질을 증가시킬 수 있는 점 등 많은 장점들을 가지지만, 기존 기지국 시스템에 비하여 여러 안테나를 사용함에 따르는 기지국 송/수신 부분의 복잡도 증가 문제와 기존 기지국과의 호환성 문제 등을 가진다.
본 발명에서는 이러한 스마트 안테나 시스템이 가지는 문제점을 해결하기 위하여 시분할 다중화 기법을 사용한 변조기 사용 및 섹터 빔 선택기와 TX 빔형성기를 사용 함으로써 다양한 섹터와 안테나 수에서도 쉽게 유연성 가지고 적용할 수 있는 스마트 안테나 기지국 변조 장치를 제공한다.

公开(公告)号：KR1020040046425A

公开(公告)日：2004-06-05

申请号：KR1020020074353

申请日：2002-11-27

Applicant: 한국전자통신연구원

Inventor： 박형일 ,  임인기 ,  정희범 ,  김종대

IPC: H01Q3/38

CPC classification number: H04B7/0854 ,  H04B7/086

Abstract: PURPOSE: A normalization apparatus is provided to reduce the size of hardware for system configuration and improve a real time processing speed. CONSTITUTION: A normalization apparatus comprises a multiplying unit for carrying out a multiplying operation required in a normalization process; a dividing unit for carrying out a dividing operation required in a normalization process through a binary log and subtracting operation; and a multiplexer(210) for synchronizing the signals received from a smart antenna receiver with a predetermined clock, and outputting the signals to the multiplying unit. The multiplying unit includes a binary log generator(220) for converting the signals input from the multiplexer into a binary log value and outputting the binary log value; a shift left(240) for outputting the output of the binary log generator into a double size; and a binary inverse log generator(250) for converting the output of the shift left into a binary inverse log value and outputting the binary inverse log value. The dividing unit includes a NORM binary log generator(270) for converting the NORM function value output from an adder into a binary log value and outputting the binary log value; a subtractor for subtracting the output of the NORM binary log generator from the output of a shift register(230); and a NORM binary inverse log generator(290) for converting the output of the subtractor into a binary inverse log value and outputting the binary inverse log value.

Abstract translation: 目的：提供一种归一化装置，以减小系统配置的硬件尺寸，提高实时处理速度。 构成：归一化装置包括：乘法单元，用于执行归一化处理中所需的乘法运算; 分割单元，用于通过二进制对数和减法运算执行归一化处理中所需的分割操作; 以及用于将从智能天线接收机接收的信号与预定时钟同步的多路复用器（210），并将该信号输出到乘法单元。 乘法单元包括用于将从多路复用器输入的信号转换成二进制对数值并输出二进制对数值的二进制对数生成器（220） 左移（240），用于将二进制日志生成器的输出输出为双倍大小; 以及用于将左移的输出转换为二进制反向对数值并输出二进制反向对数值的二进制反向对数生成器（250）。 分割单元包括NORM二进制对数发生器（270），用于将从加法器输出的NORM函数值转换为二进制对数值并输出二进制对数值; 减法器，用于从移位寄存器（230）的输出中减去所述NORM二进制对数生成器的输出; 以及用于将减法器的输出转换为二进制反向对数值并输出二进制反向日志值的NORM二进制逆对数生成器（290）。

公开(公告)号：KR100430567B1

公开(公告)日：2004-05-10

申请号：KR1020000059749

申请日：2000-10-11

Applicant: 한국전자통신연구원

Inventor： 박형일 ,  어익수 ,  김경수

IPC: H03M13/27

CPC classification number: H03M13/2782 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/276 ,  H03M13/2764

Abstract: An interleaving/deinterleaving processing method, a channel encoding system using it and a computer readable recording media for realizing it is provided. The interleaver includes: an interleaving storing unit for storing data sequence; the writing address generating unit for obtaining inter-location offset of a memory on which symbols are to be written in order to perform a writing operation and for generating a writing address to be practically written on, data and a memory control signal; an address offset generating unit for receiving a middle value (MID_OFF) and a start signal from the writing address generating unit, the middle value and the start signal being used for obtaining an offset between an inter-location offset of the memory; a reading address generating unit for generating increasing the address offset generating unit originated signal to as much as a symbol's memory inter-location offset; the first and the second selecting unit for selecting appropriate signal between a control signal and address in the writing address generating unit and the reading address generating unit transferred writing operation needed reading operation, and in a real interleaving operation needed reading operation; and a third selecting unit for selecting appropriate symbol in the memory output signals and performed from the reading address generating unit transferred interleaving.

Abstract translation: 提供了一种交错/去交错处理方法，一种使用它的信道编码系统和一种用于实现它的计算机可读记录介质。 交织器包括：交织存储单元，用于存储数据序列; 写入地址产生单元，用于获得其上将写入符号的存储器的位置间偏移，以便执行写入操作并产生将被实际写入的写入地址，数据和存储器控制信号; 地址偏移产生单元，用于从写入地址产生单元接收中间值（MID_OFF）和开始信号，中间值和开始信号用于获得存储器的位置间偏移之间的偏移; 读取地址产生单元，用于产生地址偏移产生单元产生的信号增加到符号的存储器位置间偏移; 第一选择单元和第二选择单元，用于在写入地址生成单元和读取地址生成单元传送的写入操作所需的读取操作中以及在实际交织操作所需的读取操作中选择控制信号和地址之间的适当信号; 以及第三选择单元，用于从存储器输出信号中选择适当的符号，并从读取地址生成单元传送的交织执行。

公开(公告)号：KR100402786B1

公开(公告)日：2003-10-22

申请号：KR1020010046061

申请日：2001-07-30

Applicant: 한국전자통신연구원

Inventor： 임인기 ,  박형일 ,  김경수 ,  조한진

IPC: H04B7/26

CPC classification number: H04L1/0057 ,  H04L1/0013 ,  H04L1/0017 ,  H04L1/0025 ,  H04L1/0041 ,  H04L1/0043 ,  H04L1/0068 ,  H04L1/0072 ,  H04L1/08

Abstract: In an apparatus for a TFCI mapping in a wireless communication mobile station, and a method thereof, the apparatus includes an encoding unit for encoding a TFCI transmitted from a main control unit as a CPU; a TFCI mapping unit for generating necessary control parameter and a TFCI code by using a signal encoded by the encoding unit and a signal transmitted from the CPU; and a CPU for controlling the encoding unit and the mapping unit.

Abstract translation: 在用于无线通信移动台中的TFCI映射的装置及其方法中，该装置包括：编码单元，用于编码从主控制单元作为CPU发送的TFCI; TFCI映射单元，用于通过使用由编码单元编码的信号和从CPU发送的信号来生成必要的控制参数和TFCI码; 以及用于控制编码单元和映射单元的CPU。