Abstract:
The slip detection apparatus detects slip between synchronous clock signal generated by a network reference clock board assembly and reference clock signal input to generate synchronous clock signal. the apparatus includes a master reset signal generator (1) for generating reset signal of a counter (2) according to a first comprative clock signal (VF 8 KHz), reference clock (VF), and slip detection start signals (SLS), a counter (2) for counting a second comparative clook signal by the master reset signal, a register (3) for storing the counted result, and a processor (4) for generating the slip detection start signal (SLS) transmitted to the master reset signal generator (1) and for generating read enable signal transmitted to the register (3) to read the slip detection data.
Abstract:
The disclosed are a processor visual synchronizing device of a data communication system having a plurality of processors and line interfaces, and a method thereof. According to an embodiment of the present invention, the processor visual synchronizing device includes: a first local processor which synchronizes a visual of an external device and a system by recognizing the visual difference between the external device and the system by exchanging a visual message with the external device; and a second local processor which receives information on the visual including the visual difference between the external device and the system from the first local processor synchronized with the external device on the visual, and synchronizes the first local processor and the internal visual of the system using the received information on the visual.
Abstract:
In a switching system using an N+1 switch redundancy method, a backplane connects a plurality of switch cards that are mounted in a half-slot of an upper end portion and a lower end portion of the center of a chassis and a plurality of line cards that are mounted in the half-slot of the upper end portion and the lower end portion of the chassis at both sides of the plurality of switch cards. In this case, in each line card and each switch card, a line card and a switch card of the same position are connected in the upper end portion or the lower end portion of the chassis using some connector groups, and a line card and a switch card that are disposed at the upper end portion or the lower end portion of the chassis are crossed and connected using the remaining connector groups.