-
131.
公开(公告)号:EP3732784A1
公开(公告)日:2020-11-04
申请号:EP17935989.8
申请日:2017-12-28
Applicant: INTEL Corporation
Inventor: SWAN, Johanna M. , EID, Feras , KAMGAING, Telesphor , NAIR, Vijay K. , DOGIAMIS, Georgios C. , LEUSCHNER, Stephan
-
公开(公告)号:EP3437191A1
公开(公告)日:2019-02-06
申请号:EP17776049.3
申请日:2017-01-24
Applicant: Intel Corporation
-
公开(公告)号:EP3394929A1
公开(公告)日:2018-10-31
申请号:EP15911474.3
申请日:2015-12-22
Applicant: Intel Corporation
Inventor: KAMGAING, Telesphor , DOGIAMIS, Georgios, C. , NAIR, Vijay, K.
CPC classification number: H04M1/0277 , G06F1/1613 , G06F1/1698 , H01L2223/6677 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/15311 , H01Q1/2283 , H01Q1/243 , H01Q1/38 , H01Q1/40 , H01Q1/405 , H01Q3/26 , H01Q9/0414 , H01Q21/0093 , H01Q21/22 , H01Q21/28 , H01Q23/00 , H01Q25/00
Abstract: Embodiments of the invention include a microelectronic device that includes a die having at least one transceiver unit, a redistribution package coupled to the die, and a substrate coupled to the redistribution package. The substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.
-
134.
公开(公告)号:EP2044626B1
公开(公告)日:2015-07-22
申请号:EP07799114.9
申请日:2007-06-27
Applicant: Intel Corporation
Inventor: KAMGAING, Telesphor
IPC: H01L23/538 , H01L21/768 , H01L23/48 , H01L23/58 , H01L21/8234 , H01L21/8238 , H01L21/764
CPC classification number: H01L21/823878 , H01L21/76224 , H01L21/764 , H01L21/76898 , H01L21/823481 , H01L23/481 , H01L23/585 , H01L2924/0002 , H01L2924/00
-
135.
公开(公告)号:EP2044626A1
公开(公告)日:2009-04-08
申请号:EP07799114.9
申请日:2007-06-27
Applicant: Intel Corporation
Inventor: KAMGAING, Telesphor
IPC: H01L23/538
CPC classification number: H01L21/823878 , H01L21/76224 , H01L21/764 , H01L21/76898 , H01L21/823481 , H01L23/481 , H01L23/585 , H01L2924/0002 , H01L2924/00
Abstract: The techniques described herein reduce the substrate noise current that exists when digital and analog components reside on the same microelectronic die. Single or multiple rows of isolation vias form isolation barriers between the individual circuit blocks. The isolation vias may be hollow or (lined or filled) with a conductive or non-conductive material.
-
-
-
-