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    Virtual reality/augmented reality apparatus and method
    136.
    发明授权
    Virtual reality/augmented reality apparatus and method 有权

    公开(公告)号：US10921884B2

    公开(公告)日：2021-02-16

    申请号：US16453189

    申请日：2019-06-26

    Applicant: INTEL CORPORATION

    Inventor： Tomas G. Akenine-Moller ,  Robert M. Toth ,  Ingo Wald ,  Aditya S. Yanamandra ,  Brent E. Insko ,  Michael Apodaca ,  Prasoonkumar Surti

    IPC: G06F3/01 ,  G06T15/00 ,  G06F3/14 ,  G06T1/20 ,  G06T3/00 ,  G06T19/00

    Abstract: A virtual reality apparatus and method are described. For example, one embodiment of an apparatus comprises: a compute cluster comprising global illumination circuitry and/or logic to perform global illumination operations on graphics data in response to execution of a virtual reality application and to responsively generate a stream of samples; a filtering/compression module to perform filtering and/or compression operations on the stream of samples to generate filtered/compressed samples; a network interface to communicatively couple the compute cluster to a network, the filtered/compressed samples to be streamed over the network; a render node to receive the filtered/compressed samples streamed over the network, the render node comprising: decompression circuitry/logic to decompress the filtered/compressed samples to generate decompressed samples; a sample buffer to store the decompressed samples; and sample insertion circuitry/logic to asynchronously insert samples into a light field rendered by a light field rendering circuit/logic.

    GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING
    137.
    发明申请
    GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING 有权

    公开(公告)号：US20210012452A1

    公开(公告)日：2021-01-14

    申请号：US16943984

    申请日：2020-07-30

    Applicant: Intel Corporation

    Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

    IPC: G06T1/20 ,  G06T17/10

    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

    Apparatus and method for ray tracing instruction processing and execution
    139.
    发明授权
    Apparatus and method for ray tracing instruction processing and execution 有权

    公开(公告)号：US10755469B2

    公开(公告)日：2020-08-25

    申请号：US16235838

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Karthik Vaidyanathan ,  Michael Apodaca ,  Thomas Raoux ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Joshua Barczak

    IPC: G06T15/06 ,  G06T1/60 ,  G06T9/00 ,  G06T5/00

    Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

    Early termination in bottom-up acceleration data structure refit
    140.
    发明授权
    Early termination in bottom-up acceleration data structure refit 有权

    公开(公告)号：US10740953B2

    公开(公告)日：2020-08-11

    申请号：US16235583

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Kai Xiao ,  Michael Apodaca ,  Carson Brownlee ,  Thomas Raoux ,  Joshua Barczak ,  Gabor Liktor

    IPC: G06T15/06 ,  G06T1/20

    Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

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