公开(公告)号：US20230028666A1

公开(公告)日：2023-01-26

申请号：US17379121

申请日：2021-07-19

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Prathamesh Raghunath Shinde ,  Yue Qi ,  Abhishek R. Appu ,  Xinmin Tian ,  Vasanth Ranganathan ,  Ben J. Ashbaugh

IPC: G06F9/30

Abstract: Embodiments are directed to systems and methods for performing global memory atomics in a private cache of a sub-core of a GPU. An embodiment of a GPU includes multiple sub-cores each including a load/store pipeline. The load/store pipeline is operable to receive information specifying an atomic operation to be performed within a primary data cache of the load/store pipeline. The load/store pipeline is also operable to read data to be modified by the atomic operation into the primary data cache from a memory hierarchy shared by the multiple sub-cores. The load/store pipeline is further operable to produce an atomic result of the atomic operation by modifying the data within the primary data cache based on the atomic operation.

公开(公告)号：US11508338B2

公开(公告)日：2022-11-22

申请号：US17062871

申请日：2020-10-05

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan K. Bhiravabhatla ,  Arthur D. Hunter, Jr. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G06F12/0875 ,  G06F9/46 ,  G09G5/00 ,  G06F12/084 ,  G06F12/0811

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US20220253317A1

公开(公告)日：2022-08-11

申请号：US17683564

申请日：2022-03-01

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/448

Abstract: A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

公开(公告)号：US11373269B2

公开(公告)日：2022-06-28

申请号：US16923944

申请日：2020-07-08

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06T1/60 ,  G06F12/127 ,  G06F12/0815 ,  G06F12/123

Abstract: An apparatus to facilitate cache replacement is disclosed. The apparatus includes a cache memory and cache replacement logic to manage data in the cache memory. The cache replacement logic includes tracking logic to track addresses accessed at the cache memory and replacement control logic to monitor the tracking logic and apply a replacement policy based on information received from the tracking logic.

公开(公告)号：US11354848B1

公开(公告)日：2022-06-07

申请号：US16662636

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  G06K9/00 ,  H04N5/369 ,  G06T15/60 ,  G06T15/10 ,  H04N13/239 ,  H04N13/344 ,  H04N5/232 ,  G02B27/01 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide for technology that assigns a first shading rate to a first region of a frame. The technology further assigns a second shading rate to a second region of the frame. The first shading rate indicates that the first region will be rendered at a first resolution, and the second shading rate indicates that the second region will be rendered at a second resolution less than the first resolution. The first and second shading rates are associated with a selection based on a motion vector that corresponds to motion of an object. The object is rendered as part of a scene that includes the first region rendered at the first resolution and the second region rendered at the second resolution.

公开(公告)号：US20220129271A1

公开(公告)日：2022-04-28

申请号：US17430963

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Altug Koker ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Vasanth Ranganathan

IPC: G06F9/30 ,  G06F12/0871 ,  G06F12/0811 ,  G06F7/58 ,  G06T15/06

Abstract: Methods and apparatus relating to data initialization techniques. In an example, an apparatus comprises a processor to read one or more metadata codes which map to one or more cache lines in a cache memory and invoke a random number generator to generate random numerical data for the one or more cache lines in response to a determination that the one more metadata codes indicate that the cache lines are to contain random numerical data. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220121421A1

公开(公告)日：2022-04-21

申请号：US17431034

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Lakshminarayana Striramassarma ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter ,  Prasoonkumar Surti ,  David Puffer ,  James Valerio ,  Ankur N. Shah

IPC: G06F7/575 ,  G06F7/544 ,  G06F9/30 ,  G06F9/38 ,  G06F12/128 ,  G06F12/0875 ,  G06F12/0866 ,  G06F12/0895 ,  G06F12/02

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

公开(公告)号：US11288191B1

公开(公告)日：2022-03-29

申请号：US17132147

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Aditya Navale ,  Altug Koker ,  Brandon Fliflet ,  Jeffery S. Boles ,  James Valerio ,  Vasanth Ranganathan ,  Anirban Kundu ,  Pattabhiraman K

IPC: G06F12/0802

Abstract: An apparatus to facilitate memory flushing is disclosed. The apparatus comprises a cache memory, one or more processing resources, tracker hardware to dispatch workloads for execution at the processing resources and to monitor the workloads to track completion of the execution, range based flush (RBF) hardware to process RBF commands and generate a flush indication to flush data from the cache memory and a flush controller to receive the flush indication and perform a flush operation to discard data from the cache memory at an address range provided in the flush indication.

公开(公告)号：US11269643B2

公开(公告)日：2022-03-08

申请号：US15482798

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/448

Abstract: A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

公开(公告)号：US11263141B2

公开(公告)日：2022-03-01

申请号：US17026264

申请日：2020-09-20

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.