公开(公告)号：JPH0590897A

公开(公告)日：1993-04-09

申请号：JP27348791

申请日：1991-09-26

Applicant: SONY CORP

Inventor： IKEDA YASUNARI

IPC: H03H17/00 ,  H03H17/02 ,  H05B41/282

Abstract: PURPOSE:To make it possible to enhance the oversampling processing speed by making the operating speed of each adder, multiplier, and so on constituting the digital filter circuit equal to input data speed. CONSTITUTION:A sample number converting circuit 1 in the over-sampling circuit carries out sample number conversion on input data, while the interpolation points that is obtained by the sample number conversion processing are provided with temporary reference value 0. Further, the data processing section at the even side of the digital filter circuit and the data processing section at the odd side thereof carry out the convolution arithmetic operation on each data obtained from a circuit 1, the DC correction is carried out on resulatant data using the correcting value corresponding to the essential reference value, and the output from the data processing section at the even side and the output from the data processing section at the odd side are alternately selected and output. With this constitution, the operation speed of each adder and multiplier in the data processing section at the even side and the operation speed of each adder and multiplier in the data processing section at the odd side are made equal to the input data speed, thereby carrying out the oversampling processing at doubled high speed.

公开(公告)号：JPH0575895A

公开(公告)日：1993-03-26

申请号：JP26305491

申请日：1991-09-13

Applicant: SONY CORP

Inventor： IKEDA YASUNARI

IPC: H04N5/14 ,  H04N5/52

Abstract: PURPOSE:To provide the accurate and stable automatic gain adjustment circuit for video signal not affected by drifting or the like. CONSTITUTION:The automatic gain adjustment circuit for video signal is composed of a sampling control circuit 1, a variable gain control amplifier circuit 2, an A/D converter 4, resisters 6 and 8, a signal subtraction circuit 10, a comparison circuit 12, a PNP transistor 14, a resistor 16, an NPN transistor 20, a resistor 22, capacitor 24 and a buffer circuit 26. Two different reference levels of the synchronizing signal SYNC of a video signal are held by the resisters 6 and 8, and the difference is calculated by the signal subtraction circuit 10, and an error voltage is calculated in comparison with the reference voltage from a reference voltage generation circuit 28, and the gain of the variable gain control form amplifier circuit 2 is adjusted by this error difference voltage signal. The processing is performed by a digital circuit other than the variable gain control form amplifier circuit 2, resulting in not affected by drifting.

公开(公告)号：JPH0522156A

公开(公告)日：1993-01-29

申请号：JP17557991

申请日：1991-07-16

Applicant: SONY CORP

Inventor： IKEDA YASUNARI

IPC: H03M7/42 ,  G06T9/00 ,  H04N1/41 ,  H04N7/24 ,  H04N19/00 ,  H04N19/423 ,  H04N19/85 ,  H04N19/91

Abstract: PURPOSE:To link fixed length codes having various lengths without adding any dummy space between variable length codes. CONSTITUTION:An encoding input is supplied to an encoding table (ROM) 1 for variable length encoding and a first MUX 2. The encoding table 1 converts the encoding input to a variable length code, outputs the code and outputs the code length as well. The code length output from this encoding table 1 is supplied to a second MUX 3 together with a fixed length code input to be inputted in the case of the fixed length encoding of the encoding input. By controlling the outputs of these first and second MUX 2 and 3 according to a variable length/fixed length control signal, the encoded codes and the code lengths in the respective cases are outputted. The encoded codes and the code lengths from these first and second MUX 2 and 3 are inputted to a shifter 4 and a shifter control circuit (adder 6 and register and processed so that the next code can successively follow to a certain code.

公开(公告)号：JPH0368566B2

公开(公告)日：1991-10-29

申请号：JP26479188

申请日：1988-10-20

Applicant: SONY CORP

Inventor： IKEDA YASUNARI

IPC: H03J5/02 ,  H02J7/28

公开(公告)号：JPH03201882A

公开(公告)日：1991-09-03

申请号：JP34427389

申请日：1989-12-28

Applicant: TOKYO ELECTRIC POWER CO ,  SONY CORP

Inventor： KIMURA HIROSHIGE ,  WATANABE TAKEMOTO ,  SHIMIZU HIDEO ,  IKEDA YASUNARI ,  KATSUMATA TORU

IPC: H04N5/278 ,  G09G5/24 ,  H04N5/445 ,  H04N5/66

Abstract: PURPOSE:To attain stable and easy to see display of a video signal from a storage element and convenience of use by generating an internal synchronizing signal based on a readout clock when no external video signal is inputted, supplying the generated synchronizing signal to a monitor, reading a video signal from the storage element and supplying the signal to the monitor. CONSTITUTION:A detection circuit 21 detects the presence of an external video signal fed externally. In the absence of the external video signal, an internal synchronizing signal is generated based on a readout clock generated by clock generating means 6A, 7, 8 and fed to a monitor, and a video signal is read from a storage element 9 and the only the read video signal is fed to the monitor, Where the signal is displayed. That is, the external video signal is deleted and only the video signal from the storage element 9 is displayed as if it is a character written on a blackboard.

公开(公告)号：JPH03201823A

公开(公告)日：1991-09-03

申请号：JP34427589

申请日：1989-12-28

Applicant: TOKYO ELECTRIC POWER CO ,  SONY CORP

Inventor： HATTORI SEIJI ,  SHIMIZU HIDEO ,  WATANABE TAKEMOTO ,  IKEDA YASUNARI

IPC: H04N5/14 ,  H03K5/00 ,  H03K5/007 ,  H03M1/06 ,  H03M1/12 ,  H04N5/18 ,  H04N7/00 ,  H04N19/00 ,  H04N19/132 ,  H04N19/136 ,  H04N19/182 ,  H04N19/196 ,  H04N19/85

Abstract: PURPOSE:To obtain a digital output signal to be a clamp level same as a target level by feeding a clamp error voltage back to the clamp voltage in the front stage of an A/D conversion circuit. CONSTITUTION:At the time of A>B when an input A from an A/D conversion circuit 3 is larger than an input B from an input terminal 5, a signal at an L level is obtained at an output end O1 of a comparator 21 and a signal at an H level is obtained at an output end O2. These signals are sampled by a sampling pulse and the signal at the H level is obtained at the terminals Q of flip-flop circuits 22 and 23. Then, the signal at the H level is obtained even at the terminals Q as well. A transistor 25 is turned OFF and a transistor 26 is turned ON. Then, charges accumulated at a capacitor 27 are discharged through this transistor 26. This voltage is taken out by a buffer 28, supplied through a resistor 29 to one adder 11 and added with an analog reference voltage and the clamp level is decreased. At the time of A

公开(公告)号：JPH02193485A

公开(公告)日：1990-07-31

申请号：JP1254389

申请日：1989-01-20

Applicant: TOKYO ELECTRIC POWER CO ,  SONY CORP

Inventor： HATTORI SEIJI ,  SHIMIZU HIDEO ,  BABA HIROYUKI ,  IKEDA YASUNARI ,  KATSUMATA TORU

IPC: H04N7/14

Abstract: PURPOSE:To easily and surely make a definite decision of a correct system against a person photographing camera of a face of a person who makes a telephone call by inverting the left and the right of a video signal by an inversion memory, at the time of displaying a video of a video signal from the person photographing camera on a part of a display monitor. CONSTITUTION:In the case when a second video signal for a sub-screen is a video signal of the own face from a person camera of the own video telephone system, a second digitized video signal from an A/D converter 2 is supplied to a memory 5A and a second digitized video signal of an image in which the left and the right of a screen are inverted, namely, a video of a face being in a mirror image relation to the own face is outputted to an output terminal 15 through a changeover switch 14.

公开(公告)号：JPS59201584A

公开(公告)日：1984-11-15

申请号：JP7521083

申请日：1983-04-28

Applicant: Sony Corp

Inventor： IKEDA YASUNARI ,  UMEMURA JIYUNJI

IPC: H04N3/00 ,  H04N7/01 ,  H04N11/20

CPC classification number: H04N7/01

Abstract: PURPOSE:To attain stable synchronous separation by constituting the double scanning converting circuit so that a mean value interpolation is applied during the video period of a video signal of the interlace system and a pre-interpolation during the vertical synchronizing period. CONSTITUTION:A luminance signal is written alternately in memories 51 and 52 for 1H each and also a luminance signal for 1H's share is read twice succeedingly, A luminance signal having a double horizontal frequency is outputted from a changeover switch 54. The double scanning converting signal by means of the mean value interpolation is obtained by a 1/2 delay line 57, an adder 56 and a level adjusting device 58. A changeover switch 60 is thrown to the A position of a contact during the video period of the video signal and a double scanning converting signal by the mean value interpolation is obtained at an output terminal 59. Further, the changeover switch 60 is thrown to the contact B position during the vertical synchronizing period and the double scanning converting signal subject to pre-interpolation is obtained at the output terminal 59.

Abstract translation: 目的：通过构成双扫描转换电路来实现稳定的同步分离，使得在隔行系统的视频信号的视频期间和垂直同步期间的预插补期间应用平均值内插。 构成：将亮度信号交替地写入到存储器51和52中，每个1H并且还分别读取1H份数的亮度信号两次，从切换开关54输出具有双水平频率的亮度信号。双重扫描转换信号 通过1/2延迟线57，加法器56和电平调整装置58获得平均值内插。在视频信号的视频周期期间，切换开关60被抛到接触的A位置，并且 在输出端子59处获得通过平均值内插的双扫描转换信号。此外，在垂直同步期间切换开关60被投入接触B位置，并且获得经过预插补的双重扫描转换信号 输出端子59。

公开(公告)号：JPS5940771A

公开(公告)日：1984-03-06

申请号：JP15032482

申请日：1982-08-30

Applicant: Sony Corp

Inventor： TANAKA YUTAKA ,  IKEDA YASUNARI ,  NAKANO HIROSHI

IPC: H04N7/01

CPC classification number: H04N7/012

Abstract: PURPOSE:To prevent the deterioration in the picture quality of oblique component of an oblique pattern and of the vertical resolution of a window frame pattern at the same time, by using an interpolation signal with pre-value forecasting at a region where horizontal and vertical high frequency components do not exist at the same time and using an interpolation signal with average value forecasting at the region where said components coexisted. CONSTITUTION:When a horizontal high frequency component SH exists in a video signal SNI, an absolute value output applied to a non-inverting input of a comparator 35 from an absolute value circuit 31 is higher than a level VH, and a level ''1'' signal is obtained at the output of the comparator 35. Outputs of comparators 32, 35 are applied to an AND circuit 36, and a low level ''0'' signal is obtained at the region where the horizontal and vertical high frequency components do not exist at the same time, and a high level ''1'' signal is obtained at the region where they coexist. A terminal 29c of a changeover switch 29 is connected to a terminal 29a when the output of the AND circuit 36 goes to a low level ''0'' and the terminal 29c is connected to a terminal 29b when the output goes to high level ''1'', and the video signal SNI is obtained at the region where the horizontal and vertical high frequency components of the video signal Si do not exist at the same time, and a video signal SNI* being a video signal SNI' is obtained at the region where these components coexist.

Abstract translation: 目的：为了防止倾斜图案的倾斜分量的图像质量和窗框图案的垂直分辨率同时降低，通过在水平和垂直高度的区域使用具有预测值的内插信号 频率分量在同一时间不存在，并且在所述分量共存的区域使用具有平均值预测的插值信号。 构成：当在视频信号SNI中存在水平高频分量SH时，从绝对值电路31施加到比较器35的非反相输入端的绝对值输出高于电平VH，电平“1” “信号在比较器35的输出处获得。比较器32,35的输出被施加到”与“电路36，并且在水平和垂直高频分量的区域获得低电平”0“信号 不同时存在，并且在它们共存的地区获得高水平的“1”信号。 当AND电路36的输出变为低电平“0”时，转换开关29的端子29c连接到端子29a，并且当输出达到高电平时端子29c连接到端子29b。 “1”，并且在同时不存在视频信号Si的水平和垂直高频分量的区域获得视频信号SNI，并且获得作为视频信号SNI'的视频信号SNI * 在这些组件共存的地区。

公开(公告)号：JPS5896460A

公开(公告)日：1983-06-08

申请号：JP19542781

申请日：1981-12-03

Applicant: SONY CORP

Inventor： OKADA TAKAFUMI ,  IKEDA YASUNARI ,  TANAKA YUTAKA

IPC: H04N7/01 ,  H04N5/14 ,  H04N5/208 ,  H04N5/21 ,  H04N5/44

Abstract: PURPOSE:To improve the sharpness through conversion of a video signal of interlace system into non-interlace system to receive a picture, by emphasizing a vertical high frequency component of a video signal. CONSTITUTION:A signal received at an antenna 20 is applied to a non-interlace converting circuit 24 via a video detection circuit 23 and converted to a non- interlace signal. This signal is applied to a luminance chroma separation circuit 25 and also to a chroma demodulation circuit 26 and a high frequency component emphasizing circuit 28 as chroma and luminance signals respectively. The output signal of the circuit 26 and 28 is given to a matrix circuit 27. In supplying a vertical step waveform, signals are picked up respectively at odd and even number fields from the circuit 24 and the luminance component of the signals is emphasized at an emphasis circuit 24. Thus, pre-shoot and overshoot are given for each one line, then the sharpness can be improved.