公开(公告)号：WO2007110749A3

公开(公告)日：2007-12-13

申请号：PCT/IB2007000772

申请日：2007-03-27

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  ASARO ANTONIO ,  LIU BO

Inventor： ASARO ANTONIO ,  LIU BO

IPC: G06F13/40

CPC classification number: G06F13/404

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract translation: 描述了一种用于向多个图形设备广播写入请求的系统和方法。 图形设备地址的不同地址范围与多个图形设备中的每个图形设备相关联。 当存储器地址在广播地址的特定范围内时，控制器接收针对存储器地址的写请求并且基于写请求的存储器地址生成多个图形设备地址。 当生成多个图形设备地址时，偏移量可以应用于与一个图形设备相关联的每个地址范围中的参考地址。 将写请求转发到与所生成的图形设备地址之一相关联的多个图形设备中的每个图形设备。

公开(公告)号：WO2007077520A3

公开(公告)日：2007-11-22

申请号：PCT/IB2007000006

申请日：2007-01-03

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  CALLWAY EDWARD

Inventor： CALLWAY EDWARD

IPC: G06T3/40

CPC classification number: G06T3/403 ,  G06F3/1415 ,  G06T3/4084 ,  G06T7/42 ,  G06T2207/20012 ,  G09G2360/02

Abstract: An image analyser analyses regions of an image. An image sealer may then scale the image adaptively, in dependence on the nature of region of the image being scaled. In one embodiment, adjacent pixels are analysed to determine their frequency content. This frequency analysis provides an indication of whether the pixels likely contain hard edges, discontinuities or variations typical of computer generated graphics. As a result of the analysis, the type of scaling suited for scaling the image portion containing the pixels may be assessed. Adjacent pixels having high frequency components may be scaled by a scaling circuit that introduces limited ringing. Adjacent pixels having lower frequency components may be scaled using a higher-order multi-tap scaler. Resulting scaled pixels may be formed as a blended combination of the two different scaling techniques.

Abstract translation: 图像分析仪分析图像的区域。 然后，图像缩放器可以根据正在缩放的​​图像的区域的性质自适应地缩放图像。 在一个实施例中，分析相邻像素以确定其频率内容。 该频率分析提供了像素是否可能包含计算机生成的图形的硬边缘，不连续或变化的指示。 作为分析的结果，可以评估适合于缩放包含像素的图像部分的缩放类型。 具有高频分量的相邻像素可以通过引入有限振铃的缩放电路进行缩放。 具有较低频率分量的相邻像素可以使用更高阶的多抽头缩放器进行缩放。 所得到的缩放像素可以形成为两种不同缩放技术的混合组合。

公开(公告)号：WO2007085963A3

公开(公告)日：2007-08-02

申请号：PCT/IB2007/000260

申请日：2007-01-30

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL SRL ,  SAGALOVITCH, Serguei ,  CHAN, Hing Pong ,  YURIN, Alexei

Inventor： SAGALOVITCH, Serguei ,  CHAN, Hing Pong ,  YURIN, Alexei

IPC: G06F9/48

Abstract: To provide for the processing of priority data elements between a host processor and a co- processor that exchange such data elements using a queue, the host processor determines a priority of a data element received from an application. If the priority is higher than a lowest possible priority value, at least one lower priority data element within the queue may be identified and modified thereby temporarily removing it from the queue (the co-processor skips processing modified data elements). When the priority data element is written into the queue a query packet is included that will cause the co-processor to return information regarding a last executed queued data element. Based on the returned information, the host processor can determine one or more unmodified data elements (uniquely corresponding to the one or more modified queued data elements) to be written into the queue in accordance with a sequence of the previously modified queued data elements. Thus the pre-empted queued data elements can be restored in the queue in an unmodified form.

公开(公告)号：WO2007074395A1

公开(公告)日：2007-07-05

申请号：PCT/IB2006/003815

申请日：2006-12-27

Applicant: ATI TECHNOLOGIES, INC ,  ATI INTERNATIONAL SRL ,  DE ALMEIDA, Adrian, S. ,  AHMADI, Mohammad-reza ,  YANG, Ivan, Wong, Yin ,  YAN, Hongtao

Inventor： DE ALMEIDA, Adrian, S. ,  AHMADI, Mohammad-reza ,  YANG, Ivan, Wong, Yin ,  YAN, Hongtao

IPC: G06F11/14

CPC classification number: G06F11/1441

Abstract: A co-processing unit of a system detects a fault condition associated with the co-processing unit and, upon detection, restores the processing unit using stored user context information. During normal operation, user context information used to execute operation commands are stored by the co-processing unit in memory and maintained after fault detection. A fault condition is detected when at least a portion of the processing unit is rendered non-operational due to a discharging electrostatic event. Fault conditions may be detected by receiving information by the co-processing unit indicative of a fault condition, or by checking at least one memory location associated with processing unit to determine if information stored therein indicates a fault condition. The co-processing unit returns the processing unit to a known, workable state by using the stored user context information to restore the pre-fault detection state information to the memory locations associated with the processing unit.

Abstract translation: 系统的协处理单元检测与协处理单元相关联的故障状况，并且在检测时，使用存储的用户上下文信息恢复处理单元。 在正常操作期间，用于执行操作命令的用户上下文信息由协处理单元存储在存储器中并在故障检测之后维护。 当处理单元的至少一部分由于放电静电事件而变得不可操作时，检测到故障状况。 可以通过由协处理单元接收指示故障状况的信息或者通过检查与处理单元相关联的至少一个存储位置来确定其中存储的信息是否指示故障状况来检测故障状况。 协处理单元通过使用存储的用户上下文信息将处理单元返回到已知的可操作状态，以将故障前检测状态信息恢复到与处理单元相关联的存储器位置。

公开(公告)号：WO2006126093A3

公开(公告)日：2007-02-08

申请号：PCT/IB2006001469

申请日：2006-05-29

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  PREETHAM ARCOT ,  POMIANOWSKI ANDREW ,  KADURI RAJA

Inventor： PREETHAM ARCOT ,  POMIANOWSKI ANDREW ,  KADURI RAJA

IPC: G06T5/00 ,  H04N5/21

CPC classification number: G06T5/002 ,  G06T5/009 ,  G06T2200/12 ,  G06T2207/10016 ,  G09G5/363 ,  G09G2320/02 ,  G09G2320/0261

Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.

Abstract translation: 本文描述了用于改进视频处理中的抗锯齿的系统和方法。 实施例包括系统中的多个视频处理器（VPU）。 每个VPU执行像素采样和像素中心采样（也称为多采样和超级采样）的一些组合。 每个VPU在相同的像素或像素中心执行采样，但每个VPU创建不同于其他VPU对应样本的采样。 VPU每个输出已被多采样和/或超级采样到合成器中的帧数据，该合成器合成帧数据以产生抗锯齿渲染帧。 抗锯齿渲染帧具有有效双倍的抗锯齿因子。

公开(公告)号：WO2006106428A3

公开(公告)日：2007-01-18

申请号：PCT/IB2006000973

申请日：2006-04-06

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  KRUGER W FRITZ ,  DREBIN ROBERT A ,  SMITH WADE K

Inventor： KRUGER W FRITZ ,  DREBIN ROBERT A ,  SMITH WADE K

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2212/652

Abstract: A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page table having a fixed, relatively small page size. The page table is broken into fragments made up of pages that are contiguous in physical address space and logical address space and have similar attributes. Fragments in logical address space begin on known boundaries such that the boundary indicates both a starting address of a fragment and the size of the fragment. Corresponding fragments in physical address space can begin anywhere, thus making the process transparent to physical memory. A fragment field in a page table entry conveys both fragment size and boundary information.

Abstract translation: 描述了虚拟存储器系统中的片段处理的方法和装置。 本发明的实施例包括协处理器，其包括用于访问物理存储器的虚拟存储器系统。 页表逻辑和片段处理逻辑扫描具有固定的相对小的页面大小的页表。 页表被分解成由物理地址空间和逻辑地址空间中连续的页构成的，具有相似属性的片段。 逻辑地址空间中的片段从已知边界开始，使得边界指示片段的起始地址和片段的大小。 物理地址空间中的相应片段可以从任何地方开始，从而使处理对物理内存透明。 页表条目中的片段字段传达片段大小和边界信息。

公开(公告)号：WO2006126093A2

公开(公告)日：2006-11-30

申请号：PCT/IB2006/001469

申请日：2006-05-29

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL SRL ,  PREETHAM, Arcot ,  POMIANOWSKI, Andrew ,  KADURI, Raja

Inventor： PREETHAM, Arcot ,  POMIANOWSKI, Andrew ,  KADURI, Raja

IPC: G06T5/00 ,  H04N5/21

CPC classification number: G06T5/002 ,  G06T5/009 ,  G06T2200/12 ,  G06T2207/10016 ,  G09G5/363 ,  G09G2320/02 ,  G09G2320/0261

Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.

Abstract translation: 本文描述了用于改进视频处理中的抗锯齿的系统和方法。 实施例包括系统中的多个视频处理器（VPU）。 每个VPU执行像素采样和像素中心采样（也称为多采样和超级采样）的一些组合。 每个VPU在相同的像素或像素中心执行采样，但每个VPU创建不同于其他VPU对应样本的采样。 VPU每个输出已被多采样和/或超级采样到合成器中的帧数据，该合成器合成帧数据以产生抗锯齿渲染帧。 抗锯齿渲染帧具有有效双倍的抗锯齿因子。

公开(公告)号：WO2006119303A3

公开(公告)日：2006-11-09

申请号：PCT/US2006/016863

申请日：2006-05-02

Applicant: ATI TECHNOLOGIES INC. ,  SENTHINATHAN, Ramesh

Inventor： SENTHINATHAN, Ramesh ,  FUNG, Richard ,  CHAN, Ronny

IPC: G01R19/257 ,  H03M1/56

Abstract: The present disclosure relates to apparatus and methods - for measurement of analog voltages in an integrated circuit (402). In particular, the apparatus Includes an on-chip digital-to-analog converter (418) configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit (426) configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic (436) operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

公开(公告)号：WO2006119303A2

公开(公告)日：2006-11-09

申请号：PCT/US2006016863

申请日：2006-05-02

Applicant: ATI TECHNOLOGIES INC ,  SENTHINATHAN RAMESH

Inventor： SENTHINATHAN RAMESH ,  FUNG RICHARD ,  CHAN RONNY

IPC: G01R19/257 ,  H03M1/56

CPC classification number: H03M1/1225 ,  G01R19/257 ,  H03M1/56

Abstract: The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

Abstract translation: 本公开涉及用于在集成电路中测量模拟电压的装置和方法。 特别地，该装置包括片上数模转换器，其被配置为接收可变数字输入码并输出对应于可变数字输入码的对应模拟电压。 该装置还包括片上比较器电路，其被配置为接收由数模转换器输出的模拟电压和测试模拟电压作为输入，并提供指示测试模拟电压的输出。 此外，该装置包括可用于基于比较器电路的输出来确定测试模拟电压的片上逻辑。 还公开了相应的方法。

公开(公告)号：WO2006075250A3

公开(公告)日：2006-07-20

申请号：PCT/IB2006/000173

申请日：2006-01-13

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL SRL ,  ORR, Stephen, J.

Inventor： ORR, Stephen, J.

IPC: G06F1/32

Abstract: Method and apparatus for controlling power consumption of a plug-in card or circuit module (104). Power to a circuit module (104) is controlled by a user interface (116) and power manager (114) to automatically control the power state of the circuit module (104) by, among other things, powering the module up or down using a simulated hot unplug of the module (104). The apparatus further includes use of an I/O interconnect (126) to allow the system BIOS (122) to simulate the hot unplugging of the module (104).