公开(公告)号：WO2012089335A1

公开(公告)日：2012-07-05

申请号：PCT/EP2011/006556

申请日：2011-12-23

Applicant: STMICROELECTRONICS S.R.L. ,  RONCHI, Daniele ,  TERENZI, MARCO

Inventor： RONCHI, Daniele ,  TERENZI, MARCO

IPC: G01S15/89

CPC classification number: G01S15/8925 ,  G01S7/52023 ,  G01S15/8918 ,  G01S15/8927 ,  G01S15/8993

Abstract: 4D data ultrasound imaging system (100) comprising a matrix (10) of transducer elements (3) suitable for transmitting and for receiving ultrasound signals, said transducer elements (3) being divided into sub-matrixes (21) suitable for receiving in a delayed way a same acoustic signal, a plurality of reception channels (22) with one of said reception channels (22) being associated with one of said transducer elements (3), a beamformer device (109) comprising a plurality of storage cells (111) arranged in re-phasing matrixes (112), each re-phasing matrix (1 12) being associated with a corresponding sub-matrix (21) with each row (Ri) associated with one of said transducer elements (3), said storage cells (111) comprising an input storage stage (In) that is selectively associated with a row (Ri) and a reading output stage (Out) that is selectively associated with a buffer (16); each storage cell (111) that belongs to a same column (Coi) has the input stage (In) that is dynamically activated in sequential times with respect to another storage cell (11 1) of the same column (Coi) for storing the same delayed acoustic signal, said storage cells (1 11) that belong to the same column (Coi) have the output stage (Out) that is simultaneously activated.

Abstract translation: 4D数据超声成像系统（100）包括适于发送和接收超声信号的换能器元件（3）的矩阵（10），所述换能器元件（3）被分成适合于以延迟的方式接收的子矩阵（21） 一种相同的声信号，具有一个所述接收信道（22）的多个接收信道（22）与所述换能器元件（3）中的一个相关联，包括多个存储单元（111）的波束形成装置（109） 每个重定相矩阵（112）与相应的子矩阵（21）相关联，每个行（Ri）与所述换能器元件（3）中的一个相关联，所述存储单元 （111）包括选择性地与与缓冲器（16）相关联的行（Ri）和读取输出级（Out）相关联的输入存储级（In）; 属于相同列（Coi）的每个存储单元（111）具有相对于用于存储相同列（Coi）的另一存储单元（111）的连续时间动态地激活的输入级（In） 延迟声信号，属于同一列（Coi）的所述存储单元（11）具有同时被激活的输出级（Out）。

公开(公告)号：WO2011151269A2

公开(公告)日：2011-12-08

申请号：PCT/EP2011/058766

申请日：2011-05-27

Applicant: STMICROELECTRONICS S.R.L. ,  ADRAGNA, Claudio

Inventor： ADRAGNA, Claudio

IPC: H02M3/335 ,  H02M7/217

CPC classification number: H02M3/3353 ,  H02M3/33507 ,  H02M3/33523 ,  H02M7/2176 ,  H02M2001/0022

Abstract: An integrated circuit controls a switch of a switching current regulator. The current regulator comprises primary and secondary windings where a first and a second current flow, respectively. The switch is adapted to initiate or interrupt the circulation of the first current in the primary winding. The control integrated circuit comprises a comparator configured to compare a first signal representative of said first current to a second signal and a divider circuit configured to generate said second signal as a ratio of a third signal, proportional to a voltage on the primary winding, with a voltage on a capacitor. The capacitor is charged by a further current controlled by the third signal when the second current is different from zero and is discharged through resistor when the value of said second current is substantially zero.

Abstract translation: 集成电路控制开关电流调节器的开关。 电流调节器包括分别具有第一和第二电流的初级和次级绕组。 开关适于启动或中断初级绕组中的第一电流的循环。 所述控制集成电路包括：比较器，被配置为将表示所述第一电流的第一信号与第二信号进行比较;以及分频器电路，其被配置为产生所述第二信号，所述比较器与所述初级绕组上的电压成正比的第三信号与 电容上的电压。 当第二电流不同于零时，电容器被由第三信号控制的另外的电流充电，并且当所述第二电流的值基本上为零时，通过电阻放电。

公开(公告)号：WO2011138276A3

公开(公告)日：2011-11-10

申请号：PCT/EP2011/056956

申请日：2011-05-02

Applicant: STMICROELECTRONICS S.R.L. ,  SPINI, Claudio ,  ADRAGNA, Claudio

Inventor： SPINI, Claudio ,  ADRAGNA, Claudio

IPC: H02M3/335

Abstract: An integrated control circuit of a switch is described, which is adapted to open or close a current path; said integrated circuit includes a comparator to compare a first signal with a second signal representative of the current flowing through said current path. The comparator outputs a third variable signal between a low logic level and a high logic level according to whether said second signal is lower than said first signal or vice versa; the integrated circuit has a driver to generate a signal to drive said switch in response to the third signal, and is configured to detect a spike on the leading edge of said second signal and to blank said third signal for a first blanking time period which depends on a turn-on delay of said switch and a second blanking period which depends on the duration of said spike on the leading edge of said second signal.

公开(公告)号：WO2011079883A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005932

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  RICOTTI, Giulio

Inventor： ROSSI, Sandro ,  RICOTTI, Giulio

IPC: H03K17/0416 ,  H03K17/16 ,  H03K17/74 ,  B06B1/02

CPC classification number: H03K17/74 ,  B06B1/0215 ,  H03K17/04163 ,  H03K17/161

Abstract: A transmission channel (1) is described of the type comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVPO, HVP1, HVMO, HVM1), these buffer transistors (MB1, MB2, MB3, MB4) being also connected to a clamping block (5), in turn comprising clamping transistors (MC1, MC2) connected to at least one output terminal (HVout) of this transmission channel through diodes (DC1, DC2) connected to prevent the body diodes of the clamping transistors (MC1, MC2) from conducting. Advantageously according to the invention, the transmission channel (1) comprises at least one reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4) and being inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping block (5), these circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) being in correspondence with conduction terminals of the transistors (MB l, MB2, MB3, MB4; MC1, MC2) comprised into the high voltage buffer block (4) and into the clamping block (5).

Abstract translation: 描述了包括至少一个包括缓冲晶体管（MB1，MB2，MB3，MB4）和相应的缓冲二极管（DB1，DB2，DB3，DB4）的高压缓冲块（4）的传输通道（1） 在相应的电压基准（HVPO，HVP1，HVMO，HVM1）之间，这些缓冲晶体管（MB1，MB2，MB3，MB4）也连接到钳位块（5），反过来又包括钳位晶体管（MC1，MC2） 所述传输通道的至少一个输出端子（HVout）通过连接的二极管（DC1，DC2），以防止钳位晶体管（MC1，MC2）的体二极管导通。 有利地，根据本发明，传输通道（1）包括至少一个包括二极管（DME1，DME2，DME3，DME4）的复位电路（20），并且插入在电路节点（XME1，XME2，XME3，XME4，XC1，XC2 ）和高压缓冲块（4）和钳位块（5）的这些电路节点（XME1，XME2，XME3，XME4，XC1，XC2）与晶体管（MB1，MB2， MB3，MB4; MC1，MC2）组成高压缓冲块（4）并进入夹紧块（5）。

公开(公告)号：WO2011076910A1

公开(公告)日：2011-06-30

申请号：PCT/EP2010/070608

申请日：2010-12-22

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS (MALTA) LTD ,  FORMOSA, Kevin ,  AZZOPARDI, Mark Anthony ,  CORTESE, Mario Francesco

Inventor： FORMOSA, Kevin ,  AZZOPARDI, Mark Anthony ,  CORTESE, Mario Francesco

IPC: H04R19/00 ,  B81B7/00

CPC classification number: H04R19/005 ,  B81B2201/0257 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/093 ,  B81C1/0023 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/8592 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/16151 ,  H01L2924/3025 ,  Y10T29/49117 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A MEMS transducer (1) has a micromechanical sensing structure (10) and a package (46). The package (46) is provided with a substrate (45), carrying first electrical-connection elements (47), and with a lid (25), coupled to the substrate to define an internal cavity (24), in which the micromechanical sensing structure (10) is housed. The lid (25) is formed by: a cap layer (20) having a first surface (20a) and a second surface (20b), set opposite to one another, the first surface (20a) defining an external face of the package (46) and the second surface (20b) facing the substrate (45) inside the package (46); and a wall structure (21), set between the cap layer (20) and the substrate (45), and having a coupling face (21a) coupled to the substrate (45). At least a first electrical component (10, 11) is coupled to the second surface (20b) of the cap layer (20), inside the package (46), and the coupling face (21a) of the wall structure (21) carries second electrical-connection elements (30), electrically connected to the first electrical component (10, 11) and to the first electrical-connection elements (47).

Abstract translation: MEMS传感器（1）具有微机械感测结构（10）和封装（46）。 封装（46）设置有承载第一电连接元件（47）的衬底（45），以及耦合到衬底以限定内部空腔（24）的盖（25），其中微机械感测 结构（10）被容纳。 盖（25）由以下部分形成：盖层（20），具有彼此相对设置的第一表面（20a）和第二表面（20b），所述第一表面（20a）限定包装的外表面 46）和所述第二表面（20b）面对所述衬底（45）; 以及设置在所述盖层（20）和所述基板（45）之间并且具有联接到所述基板（45）的联接面（21a）的壁结构（21）。 至少第一电气部件（10,11）在封装（46）的内部联接到盖层（20）的第二表面（20b），并且壁结构（21）的联接面（21a）承载 电连接到第一电气部件（10,11）和第一电连接元件（47）的第二电连接元件（30）。

公开(公告)号：WO2010076187A3

公开(公告)日：2010-07-08

申请号：PCT/EP2009/067156

申请日：2009-12-15

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

IPC: H01L23/66 ,  H01L23/48 ,  H01L21/66 ,  H01L23/544 ,  H01L25/065

Abstract: An integrated electronic device (1) having a body (9) of semiconductor material and a first antenna (3;3a) which enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna (3b,3c). The integrated electronic device (1) has a first via (4;4a- 4d;50;50a;53) of magnetic material arranged at least in part inside the body (9), which forms, in use, a communication channel between the first antenna (3;3a) and the further antenna (3b,3c).

公开(公告)号：WO2010046724A1

公开(公告)日：2010-04-29

申请号：PCT/IB2008/003660

申请日：2008-10-22

Applicant: STMICROELECTRONICS (GRENOBLE) SAS ,  STMICROELECTRONICS S.R.L. ,  TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

Inventor： TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

IPC: G05B19/418 ,  G01R31/28

CPC classification number: G05B19/41875 ,  G01R31/2894 ,  Y02P90/22 ,  Y02P90/86

Abstract: The invention relates to a method for an improved checking of repeatability and reproducibility of a measuring chain, in particular for the quality control by means of the semiconductor device testing, wherein testing steps are provided for multiple and different devices to be subjected to measurement through a measuring system comprising at least one concatenation of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement. Advantageously, the method comprises the following steps: checking repeatability and reproducibility of each type of unit that forms part of the measuring chain of the concatenation; then making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement.

Abstract translation: 本发明涉及一种用于改进测量链的重复性和再现性检查的方法，特别是通过半导体器件测试进行质量控制的方法，其中为多个和不同的器件提供测试步骤以通过 测量系统包括测试装置（ATE）和待测量的每个装置之间的测量单元的至少一个级联。 有利地，该方法包括以下步骤：检查构成级联测量链的一部分的每种类型的单元的重复性和重复性; 然后在各测量链之间进行整体的相关性，以检查重复性和再现性，使用相应的测量装置。

公开(公告)号：WO2008064994A1

公开(公告)日：2008-06-05

申请号：PCT/EP2007/062246

申请日：2007-11-13

Applicant: STMICROELECTRONICS S.R.L. ,  MAURO, Sergio Riccardo ,  FABIANO, Sergio

Inventor： MAURO, Sergio Riccardo ,  FABIANO, Sergio

IPC: H04L25/49

CPC classification number: H04L25/49

Abstract: A regulation and shaping circuit comprising a first input terminal (405) for receiving a first input signal (Vref) with a first frequency; a second input terminal (410) for receiving a second input signal (Vin1) with a second frequency higher than the first frequency; a first circuital branch (420) coupled to the first input terminal and, through first coupling means (Z2) active at the first frequency, to an output terminal (415) for providing an output signal (Vout1); a second circuital branch (425) coupled to the second input terminal and to the output terminal, wherein said second circuital branch comprises a negative feedback circuital loop (430, 435) adapted to control the output signal according to the second input signal.

Abstract translation: 一种调节和整形电路，包括用于接收具有第一频率的第一输入信号（Vref）的第一输入端（405） 用于接收具有高于第一频率的第二频率的第二输入信号（Vin1）的第二输入端（410） 耦合到第一输入端的第一电路分支（420），以及通过第一频率的第一耦合装置（Z2）连接到用于提供输出信号（Vout1）的输出端（415）; 耦合到第二输入端和输出端的第二电路分支（425），其中所述第二电路分支包括适于根据第二输入信号控制输出信号的负反馈电路回路（430,435）。

公开(公告)号：WO2008018095A1

公开(公告)日：2008-02-14

申请号：PCT/IT2006/000607

申请日：2006-08-07

Applicant: STMicroelectronics s.r.l. ,  ADRAGNA Claudio

Inventor： ADRAGNA Claudio

IPC: G05F1/70 ,  H02M1/00

CPC classification number: G05F1/70

Abstract: A control device for a power factor correction device in forced switching power supplies is disclosed; the device for correcting the power factor comprises a converter (20) and said control device (1) is coupled with the converter to obtain from an input alternating line voltage (Vin) a regulated output voltage (Vout). The converter (20) comprises a power transistor (M) and the control device (1) comprises a driving circuit (3, 4, 6, 10) of said power transistor; the driving circuit comprises a timer (130) suitable for setting the switch-off period of said power transistor (M). The timer is coupled with the alternating line voltage (Vin) in input to the converter and is suitable for determining the switch-off period of the power transistor in function of the value of the alternating line voltage (Vin) in input to the converter.

Abstract translation: 公开了一种用于强制开关电源中的功率因数校正装置的控制装置; 用于校正功率因数的装置包括转换器（20），并且所述控制装置（1）与转换器耦合以从输入交流线电压（Vin）获得调节输出电压（Vout）。 所述转换器（20）包括功率晶体管（M），所述控制装置（1）包括所述功率晶体管的驱动电路（3,4,6,10） 所述驱动电路包括适于设置所述功率晶体管（M）的关断周期的定时器（130）。 定时器与输入到转换器的交流线路电压（Vin）耦合，适用于根据输入到转换器的交流线路电压（Vin）的值来确定功率晶体管的关断周期。

公开(公告)号：WO2008012342A1

公开(公告)日：2008-01-31

申请号：PCT/EP2007/057706

申请日：2007-07-26

Applicant: STMICROELECTRONICS S.R.L. ,  PELLIZZER, Fabio ,  BEZ, Roberto ,  BEDESCHI, Ferdinando ,  GASTALDI, Roberto

Inventor： PELLIZZER, Fabio ,  BEZ, Roberto ,  BEDESCHI, Ferdinando ,  GASTALDI, Roberto

IPC: H01L27/24 ,  G11C16/02

CPC classification number: G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144

Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

Abstract translation: 一种具有由相变存储元件（3）和选择开关（4）形成的存储单元（2）的相变存储器件。 由自己的相变存储元件（3）和自己的选择开关（4）形成的参考单元（2a）与待读取的存储单元组（7）相关联。 将该组存储器单元的电量与参考单元的类似电量进行比较，由此补偿存储单元的特性中的任何漂移。