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公开(公告)号：US20170115359A1
公开(公告)日：2017-04-27
申请号：US15076955
申请日：2016-03-22
Applicant: STMicroelectronics (Alps) SAS
Inventor： Bruno LEDUC , Pascal BERNON , Stephane CLIN
CPC classification number: G01R31/40 , G01R3/00 , G01R15/14 , G01R19/165
Abstract: A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.
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公开(公告)号：US20160233896A1
公开(公告)日：2016-08-11
申请号：US14961996
申请日：2015-12-08
Inventor： Julien SAADE , Abdelaziz GOULAHSEN
CPC classification number: H04B1/04 , G06F13/4282 , H04L25/4908
Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.
Abstract translation: 本发明涉及一种用于串行数据传输的方法，包括以下步骤：计算待发送的比特流的运行差异（RD）; 当运行视差达到阈值（T）时，计算流的后续帧（S）上的点差异; 如果点视差具有与阈值相同的符号，则反转发送的比特流中的帧的比特的状态; 并且向所发送的比特流插入具有信号反转的状态的极性比特。
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公开(公告)号：US20160224042A1
公开(公告)日：2016-08-04
申请号：US14868095
申请日：2015-09-28
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
IPC: G05F1/575
CPC classification number: G05F1/575 , H02J1/02 , H02J7/0068 , H02J7/34 , H03K19/0016
Abstract: The present disclosure relates to a voltage regulation circuit including a first transistor connected between an input of voltage to be regulated and an output of a regulated voltage. A first regulation loop controls the first transistor according to a difference between a reference voltage and a first feedback voltage derived from the regulated voltage. A second transistor is connected in series between the first transistor and the output. A second regulation loop controls the second transistor according to a difference between the reference voltage and a second feedback voltage derived from the regulated voltage. The second regulation loop is active in low and high power regulation modes. A switch circuit forces the first transistor into an on state in a low power regulation mode.
Abstract translation: 本公开涉及一种电压调节电路，其包括连接在待调节电压的输入和调节电压的输出之间的第一晶体管。 第一调节环路根据参考电压和从调节电压导出的第一反馈电压之间的差来控制第一晶体管。 第二晶体管串联连接在第一晶体管和输出端之间。 第二调节环路根据参考电压和从调节电压导出的第二反馈电压之间的差来控制第二晶体管。 第二个调节回路在低功率和高功率调节模式下有效。 开关电路迫使第一晶体管处于低功率调节模式的导通状态。
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公开(公告)号：US20160182999A1
公开(公告)日：2016-06-23
申请号：US14838437
申请日：2015-08-28
Applicant: STMicroelectronics (Alps) SAS
Inventor： Christian FRAISSE , Angelo NAGARI
Abstract: A circuit may include an audio amplifier (314) configured to amplify an input signal (SAUDIO) to generate an output signal (SOUT+, SOUT−) suitable for driving a loud speaker (316). A first circuit (318) may be configured to generate a first analog signal (SI) based on a current level drawn by the loud speaker (316), and a second circuit (320) may be configured to generate a second analog signal (SV) based on a voltage supplied across the loud speaker (316). A third circuit (322, 312) may be configured to generate a third analog signal (RESIDUE) based on the difference between the first and second analog signals, and modify the input signal (SAUDIO) based on the third analog signal.
Abstract translation: 电路可以包括被配置为放大输入信号（SAUDIO）以产生适于驱动扬声器（316）的输出信号（SOUT +，SOUT-）的音频放大器（314）。 第一电路（318）可以被配置为基于由扬声器（316）绘制的电流电平来产生第一模拟信号（SI），并且第二电路（320）可以被配置为产生第二模拟信号（SV） ）基于提供在扬声器（316）上的电压。 第三电路（322,312）可以被配置为基于第一和第二模拟信号之间的差产生第三模拟信号（RESIDUE），并且基于第三模拟信号修改输入信号（SAUDIO）。
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公开(公告)号：US12212320B2
公开(公告)日：2025-01-28
申请号：US18296325
申请日：2023-04-05
Applicant: STMICROELECTRONICS S.r.l. , STMICROELECTRONICS (ALPS) SAS
Inventor： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Thomas Jouanneau
IPC: H03K19/20 , H03K19/0185
Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.
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Patent Agency Ranking
公开(公告)号：US12124815B2
公开(公告)日：2024-10-22
申请号：US17747101
申请日：2022-05-18
Inventor： Pierre Gobin , Jeremy Ribeiro De Freitas
Abstract: A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.
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公开(公告)号：US20240243712A1
公开(公告)日：2024-07-18
申请号：US18411748
申请日：2024-01-12
Applicant: STMicroelectronics (Alps) SAS
Inventor： Vratislav MICHAL , Samuel FOULON
CPC classification number: H03F3/45183 , H03F1/3205 , H03F3/45744
Abstract: A differential pair circuit includes a first branch and a second branch having a common first node. Each of the first and second branches includes at least one transistor having a conduction node directly connected to the common first node. A third branch couples the common first node to a power supply node. The third branch includes a current source in series with a resistive element.
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公开(公告)号：US20240231410A9
公开(公告)日：2024-07-11
申请号：US18379262
申请日：2023-10-12
Inventor： Julien GOULIER , Nicolas GOUX , Marc JOISSON
CPC classification number: G05F3/262 , G05F1/468 , H03K17/18 , H03K17/22 , H03F3/45179
Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.
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公开(公告)号：US12008244B2
公开(公告)日：2024-06-11
申请号：US17810093
申请日：2022-06-30
Applicant: STMicroelectronics (Alps) SAS
Inventor： Jawad Benhammadi
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679
Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.
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公开(公告)号：US20240171424A1
公开(公告)日：2024-05-23
申请号：US18509618
申请日：2023-11-15
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Application GmbH , STMicroelectronics (Alps) SAS
Inventor： Fred Rennig , Giovanni Luca Torrisi , Manuel Gaertner , Philippe Sirito-Olivier , Fritz Burkhardt , Aldo Occhipinti
IPC: H04L12/40
CPC classification number: H04L12/40006 , H04L2012/40215
Abstract: A vehicle communication network includes electronic control units arranged in a plurality of groups. The electronic control units pertaining to the same group are coupled to each other via a respective dedicated communication bus. A central controller is coupled to the plurality of local controllers. Electrical loads are coupled to one of the electronic control units. Each of the electronic control units is configured to decode the received CAN frame to produce the actuation signal for a respective electrical load in response to a CAN frame being received from the respective local controller and transmit a CAN wake-up frame to the respective local controller and encode the feedback signal into a CAN frame for transmission to the respective local controller in response to the feedback signal being received from the respective electrical load.
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