公开(公告)号：US12160256B2

公开(公告)日：2024-12-03

申请号：US17559592

申请日：2021-12-22

Applicant: XILINX, INC.

Inventor： Chi Fung Poon ,  Chuen-Huei Chou ,  Weerachai Neeranartvong ,  Kevin Zheng

IPC: H04B1/04 ,  H03M1/66 ,  H03M1/74

Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

公开(公告)号：US20240396638A1

公开(公告)日：2024-11-28

申请号：US18202512

申请日：2023-05-26

Applicant: XILINX, INC.

Inventor： Adebabay M. BEKELE ,  Mayank RAJ ,  Chuan XIE ,  Sandeep KUMAR ,  Zhaowen WANG ,  Sukruth PATTANAGIRI GIRIYAPPA ,  Parag UPADHYAYA ,  Yohan FRANS

IPC: H04B10/54 ,  H04B10/50 ,  H04B10/508

Abstract: Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a first data pattern to an optical modulator device. The method also includes determining, while transmitting the first data pattern and for each heater control value of a plurality of heater control values for a heater, a photodiode current value associated with the optical modulator device to generate a plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based at least in part on the plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes controlling the heater for the optical modulator device based on the maximum optical modulation amplitude.

公开(公告)号：US20240396550A1

公开(公告)日：2024-11-28

申请号：US18200432

申请日：2023-05-22

Applicant: XILINX, INC.

Inventor： Wenyi SONG ,  Shadi BARAKAT

IPC: H03K19/003 ,  G11C11/408 ,  H03K3/037 ,  H03K19/0185

Abstract: Driver circuitry for memory controller circuitry includes level shifter circuitry, inverter circuitry, and output circuitry. The level shifter circuitry receives an input data signal and outputs a first level shifted data signal and a second level shifted data signal based on the input data signal. The inverter circuitry is connected to the level shifter circuitry, receives the first level shifted data signal and the second level shifted data signal, and outputs a first inverted data signal via a first output node and a second inverted data signal via a second output node. The inverter circuitry includes mitigation circuitry coupled to the first output node and the second output node and alters one or more of the first inverted data signal and the second inverted data signal. The output circuitry outputs an output data signal based on the first inverted data signal and the second inverted data signal.

公开(公告)号：US12147379B2

公开(公告)日：2024-11-19

申请号：US18089780

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Rajeev Patwari ,  Jorn Tuyls ,  Elliott Delaye ,  Xiao Teng ,  Ephrem Wu

IPC: G06F15/78 ,  G06F13/28

Abstract: Examples herein describe techniques for performing parallel processing using a plurality of processing elements (PEs) and a controller for data that has data dependencies. For example, a calculation may require an entire row or column to be summed, or to determine its mean. The PEs can be assigned different chunks of a data set (e.g., a tensor set, a column, or a row) for processing. The PEs can use one or more tokens to inform the controller when they are done with partial processing of their data chunks. The controller can then gather the partial results and determine an intermediate value for the data set. The controller can then distribute this intermediate value to the PEs which then re-process their respective data chunks using the intermediate value to generate final results.

公开(公告)号：US12124323B2

公开(公告)日：2024-10-22

申请号：US17883379

申请日：2022-08-08

Applicant: XILINX, INC.

Inventor： Ahmad R. Ansari ,  David P. Schultz ,  Felix Burton ,  Jeffrey Cuppett

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/0763 ,  G06F9/30101 ,  G06F11/0772

Abstract: Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.

公开(公告)号：US20240346220A1

公开(公告)日：2024-10-17

申请号：US18134497

申请日：2023-04-13

Applicant: XILINX, INC.

Inventor： Martin L. VOOGEL

IPC: G06F30/347

CPC classification number: G06F30/347

Abstract: Embodiments herein describe arranging TX and RX circuitry in ICs such that rotated and mirrored ICs are aligned when connected in a multiple-chip device. In one embodiment, the TX circuitry (e.g., TX physical layer or PHY) is arranged in one row while the RX circuitry (e.g., RX physical layer or PHY) is arranged in another row. As such, when an IC is rotated or mirrored, at least one TX PHY is aligned with a RX PHY on the other IC. As such, non-crossing chip-to-chip connections can be formed through the interposer.

公开(公告)号：US20240345979A1

公开(公告)日：2024-10-17

申请号：US18642714

申请日：2024-04-22

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN

IPC: G06F13/40 ,  G06F9/48

CPC classification number: G06F13/4068 ,  G06F9/4881

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

公开(公告)号：US20240333270A1

公开(公告)日：2024-10-03

申请号：US18128945

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Riyas Noorudeen REMLA ,  Showi-Min SHEN

IPC: H03K5/01

CPC classification number: H03K5/01 ,  H03K2005/00078 ,  H03K2005/00286

Abstract: Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.

公开(公告)号：US20240330558A1

公开(公告)日：2024-10-03

申请号：US18193197

申请日：2023-03-30

Applicant: Xilinx, Inc.

Inventor： Jichun Wang ,  Wuxi Li ,  Chun Zhang ,  Paul Kundarewich ,  John Blaine

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.

公开(公告)号：US20240321702A1

公开(公告)日：2024-09-26

申请号：US18474166

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Yan Wang ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Omar Zia ,  John Wuu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3675 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/32146 ,  H01L2224/32165 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/351

Abstract: A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.