公开(公告)号：US20170025380A1

公开(公告)日：2017-01-26

申请号：US14918189

申请日：2015-10-20

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L25/00 ,  H01L21/311 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/182 ,  H01L2224/83005

Abstract: Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

Abstract translation: 描述了半导体封装和扇出芯片堆叠过程。 在一个实施例中，封装包括第一级管芯和从第一级管芯的前侧突出的一排导电柱。 第二级有源管芯附接到第一级管芯的前侧，并且再分配层（RDL）形成在与该行导电柱和第二级有源管芯的前侧电接触。

公开(公告)号：US20170018497A1

公开(公告)日：2017-01-19

申请号：US15018951

申请日：2016-02-09

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L25/16 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2224/81

Abstract: In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit may include a plurality of wiring layers. At least one metal-insulator-metal (MIM) capacitor may be formed within the plurality of wiring layers. The integrated circuit may include a circuit. The circuit may include at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die. The circuit may be coupled substantially below at least a portion of the MIM capacitor in the plurality of layers. The circuit may be electrically coupled to the capacitor through the plurality of wiring layers. The integrated circuit may include a plurality of electrical connectors, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit.

Abstract translation: 在一些实施例中，方法和/或系统可以包括集成电路。 集成电路可以包括半导体管芯。 集成电路可以包括多个布线层。 可以在多个布线层内形成至少一个金属 - 绝缘体金属（MIM）电容器。 集成电路可以包括电路。 电路可以包括至少一个电感器和电压调节器，其与MIM电容器一起形成用于半导体管芯的电压调节器。 电路可以在多层中的MIM电容器的至少一部分基本上被耦合。 电路可以通过多个布线层电耦合到电容器。 集成电路可以包括多个电连接器，多个电连接器在与电路占据的第二表面的区域分开的点处耦合到第二表面。

公开(公告)号：US20160278671A1

公开(公告)日：2016-09-29

申请号：US15181229

申请日：2016-06-13

Applicant: Apple Inc.

Inventor： Milind S. Bhagavat ,  Jun Zhai

IPC: A61B5/1172 ,  G06K9/00 ,  A61B5/053

CPC classification number: A61B5/1172 ,  A61B5/053 ,  A61B2562/0214 ,  A61B2562/182 ,  G06K9/0002 ,  H01L27/14634 ,  H01L27/14636

Abstract: A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

Abstract translation: 传感器包括形成在基板的第一侧上的传感器阵列和至少一个可操作地与形成在基板的第二侧上的传感器阵列通信的电路。 至少一个通孔延伸穿过衬底以将传感器阵列电连接到至少一个电路。 将至少一个电路放置在基板的第二侧上，使得传感器阵列基本上占据基板的所有第一侧。

公开(公告)号：US20160260695A1

公开(公告)日：2016-09-08

申请号：US14637109

申请日：2015-03-03

Applicant: Apple Inc.

Inventor： Chih-Ming Chung ,  Jun Zhai ,  Yizhang Yang

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/14 ,  H01L24/19 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL），第一和第二RDL之间的堆叠管芯，以及在RDL之间延伸的导电柱。 模塑料可以将堆叠的管芯和导电柱塞在第一和第二RDL之间。

公开(公告)号：US20160218094A1

公开(公告)日：2016-07-28

申请号：US15087200

申请日：2016-03-31

Applicant: Apple Inc.

Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Abstract translation: 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。

公开(公告)号：US09318474B2

公开(公告)日：2016-04-19

申请号：US14192145

申请日：2014-02-27

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Yizhang Yang ,  Mengzhi Pang

IPC: H01L23/34 ,  H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L25/165 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649

Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The semiconductor device package assembly may include a first die electrically connected to the first substrate such that the first die is directly bonded to the first substrate. The semiconductor device package assembly may include a second substrate directly bonded to a surface of the first die. The semiconductor device package assembly may include an electronic memory module. The electronic memory module may be directly bonded to the second substrate. The semiconductor device package assembly may include a thermally conductive material directly applied to the electronic memory module. The semiconductor device package assembly may include a heat spreader directly bonded to the thermally conductive material. The heat spreader may function to transfer heat from the first die and the electronic memory module through the heat spreader from the first side to the second side.

Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 半导体器件封装组件可以包括电连接到第一衬底的第一裸片，使得第一裸片直接结合到第一衬底。 半导体器件封装组件可以包括直接接合到第一管芯的表面的第二衬底。 半导体器件封装组件可以包括电子存储器模块。 电子存储器模块可以直接结合到第二衬底。 半导体器件封装组件可以包括直接施加到电子存储器模块的导热材料。 半导体器件封装组件可以包括直接结合到导热材料的散热器。 散热器可以起到将热量从第一模具和电子存储器模块通过散热器从第一侧传递到第二侧的功能。

公开(公告)号：US09305959B2

公开(公告)日：2016-04-05

申请号：US14294903

申请日：2014-06-03

Applicant: Apple Inc.

Inventor： Milind S. Bhagavat ,  Jun Zhai

IPC: G06K9/00 ,  H01L27/146

CPC classification number: G06K9/0002 ,  H01L27/14634 ,  H01L27/14636

Abstract: A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

Abstract translation: 传感器包括形成在基板的第一侧上的传感器阵列和至少一个可操作地与形成在基板的第二侧上的传感器阵列通信的电路。 至少一个通孔延伸穿过衬底以将传感器阵列电连接到至少一个电路。 将至少一个电路放置在基板的第二侧上，使得传感器阵列基本上占据基板的所有第一侧。

公开(公告)号：US09305853B2

公开(公告)日：2016-04-05

申请号：US14088736

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H01L23/52 ,  H01L29/40 ,  H01L23/28 ,  H01L23/12 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/12 ,  H01L23/481 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

Abstract translation: 用于PoP（封装封装）的底部封装可以形成有支撑薄的或无芯的衬底的加强层。 加强层可以为基底提供刚度和刚度，以增加底部包装的刚度和刚性，并提供更好的基底处理。 加强层可以使用芯材，层压层和金属层形成。 衬底可以形成在加强层上。 加强层可以包括尺寸适于容纳模具的开口。 裸片可以在开口中耦合到衬底的暴露表面。 通过加强层的金属填充的通孔可以用于将衬底耦合到顶部封装。

公开(公告)号：US20150118795A1

公开(公告)日：2015-04-30

申请号：US14593317

申请日：2015-01-09

Applicant: APPLE INC.

Inventor： Jie-Hua Zhao ,  Yizhang Yang ,  Jun Zhai ,  Chih-Ming Chung

IPC: H01L25/00 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y02P80/30 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.

Abstract translation: PoP（封装封装）封装包括一个耦合到顶部封装的底部封装。 底部封装顶部的端子通过位于底部封装的上表面和顶部封装的下表面之间的电绝缘材料耦合到顶部封装的底部上的端子。 底部包装和顶部包装在加工包装的过程中被联接，该过程中施加力以使包装在一起。

公开(公告)号：US08963311B2

公开(公告)日：2015-02-24

申请号：US13627905

申请日：2012-09-26

Applicant: Apple Inc.

Inventor： Jie-Hua Zhao ,  Yizhang Yang ,  Jun Zhai ,  Chih-Ming Chung

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y02P80/30 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.

Abstract translation: PoP（封装封装）封装包括一个耦合到顶部封装的底部封装。 底部封装顶部的端子通过位于底部封装的上表面和顶部封装的下表面之间的电绝缘材料耦合到顶部封装的底部上的端子。 底部包装和顶部包装在加工包装的过程中被联接，该过程中施加力以使包装在一起。