公开(公告)号：US11158607B2

公开(公告)日：2021-10-26

申请号：US16503806

申请日：2019-07-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US09679187B2

公开(公告)日：2017-06-13

申请号：US14741831

申请日：2015-06-17

Applicant: Apple Inc.

Inventor： Milind S. Bhagavat ,  Patrick E. O'Brien ,  Jun Zhai ,  Dale R. Setlak ,  David D. Coons ,  Kwan-Yu Lai

IPC: G06K9/00

CPC classification number: G06K9/00053

Abstract: A finger biometric sensor assembly may include a finger biometric sensor integrated circuit (IC) die having a finger sensing area and a cover layer aligned with the finger sensing area. The finger biometric sensor may also include a direct bonding interface between the finger biometric sensor and the cover layer.

公开(公告)号：US20170053897A1

公开(公告)日：2017-02-23

申请号：US14935310

申请日：2015-11-06

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L21/683 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7684 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/181 ,  H01L2924/186

Abstract: Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.

Abstract translation: 描述了封装和3D裸片堆叠过程。 在一个实施例中，封装包括结合到包括封装在氧化物层中的第一级管芯的第一封装级的第二级管芯晶体管和延伸穿过氧化物层的多个通孔氧化物通孔（TOV）。 在一个实施例中，TOV和第一级模具具有大约20微米或更小的高度。

公开(公告)号：US20250157991A1

公开(公告)日：2025-05-15

申请号：US19023053

申请日：2025-01-15

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/60 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US09633974B2

公开(公告)日：2017-04-25

申请号：US14638925

申请日：2015-03-04

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Kwan-Yu Lai ,  Mengzhi Pang ,  Chonghua Zhong ,  Se Young Yang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

公开(公告)号：US20170025380A1

公开(公告)日：2017-01-26

申请号：US14918189

申请日：2015-10-20

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L25/00 ,  H01L21/311 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/182 ,  H01L2224/83005

Abstract: Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

Abstract translation: 描述了半导体封装和扇出芯片堆叠过程。 在一个实施例中，封装包括第一级管芯和从第一级管芯的前侧突出的一排导电柱。 第二级有源管芯附接到第一级管芯的前侧，并且再分配层（RDL）形成在与该行导电柱和第二级有源管芯的前侧电接触。

公开(公告)号：US11881678B1

公开(公告)日：2024-01-23

申请号：US17015766

申请日：2020-09-09

Applicant: Apple Inc.

Inventor： Michael J. Bishop ,  Kwan-Yu Lai ,  Alex Goldis ,  Alfredo Bismuto ,  Jeffrey Thomas Hill

IPC: H01S5/00 ,  H01S5/40 ,  G02B3/06 ,  G02B26/08 ,  G02B26/10 ,  G02B6/12

CPC classification number: H01S5/0071 ,  G02B3/06 ,  G02B6/12 ,  G02B26/0833 ,  G02B26/105 ,  H01S5/4043 ,  H01S5/4087

Abstract: Configurations for a photonics assembly and the operation thereof are disclosed. The photonics assembly may include multiple photonics dies which may be arranged in an offset vertical stack. The photonics dies may emit light, and in some examples, an optical element may be a detector for monitoring properties such as the wavelength of the light. The photonics dies may be arranged in a stack as a package and the packages may be stacked or arranged side by side or both for space savings. The PIC may include combining and/or collimating optics to receive light from the photonics dies, a mirror to redirect the light, and an aperture structure. The aperture structure may include a region which is at least partially transparent such that light transmits through the transparent region of the aperture structure. The aperture structure may include an at least partially opaque region which may be used for directing and/or controlling the light launch position.

公开(公告)号：US20220013504A1

公开(公告)日：2022-01-13

申请号：US17484188

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20180082858A1

公开(公告)日：2018-03-22

申请号：US15826509

申请日：2017-11-29

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Flynn P. Carson ,  Kwan-Yu Lai

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L23/31 ,  H05K3/46

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5225 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4682 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

公开(公告)号：US09899239B2

公开(公告)日：2018-02-20

申请号：US14935292

申请日：2015-11-06

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Flynn P. Carson ,  Kwan-Yu Lai

IPC: H05K3/02 ,  H05K3/10 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H05K3/46

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4682 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.