公开(公告)号：US11307787B2

公开(公告)日：2022-04-19

申请号：US15826051

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Alberto J. Munoz

IPC: G06F15/173 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L67/10 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  G06F9/455 ,  H03M7/30 ,  H03M7/40 ,  H04L43/08 ,  H04L47/20 ,  H04L47/2441 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L61/5007 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L41/044 ,  H04L49/104 ,  H04L67/63 ,  H04L67/75 ,  H04L43/04 ,  H04L43/06 ,  H04L43/0894 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  H04L67/1014 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H05K7/14 ,  H04L47/78 ,  G06F11/14 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L29/06 ,  G06F15/80

Abstract: Technologies for generating manifest data for a sled include a sled to generate manifest data indicative of one or more characteristics of the sled (e.g., hardware resources, firmware resources, a configuration of the sled, or a health of sled components). The sled is also to associate an identifier with the manifest data. The identifier uniquely identifies the sled from other sleds. Additionally, the sled is to send the manifest data and the associated identifier to a server. The sled may also detect a change in the hardware resources, firmware resources, the configuration, or component health of the sled. The sled may also generate an update of the manifest data based on the detected change, where the update specifies the detected change in the hardware resources, firmware resources, the configuration, or component health of the sled. The sled may also send the update of the manifest data to the server.

公开(公告)号：US11290392B2

公开(公告)日：2022-03-29

申请号：US15620376

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Mohan J. Kumar ,  Donald L. Faw ,  Susanne M. Balle ,  Narayan Ranganathan

IPC: H04L12/927 ,  H04L29/08 ,  H04L12/933 ,  H04L12/865 ,  H04L47/80 ,  H04L67/00 ,  H04L49/109 ,  H04L67/1097 ,  H04L47/6275

Abstract: Technologies for pooling accelerators over fabric are disclosed. In the illustrative embodiment, an application may access an accelerator device over an application programming interface (API) and the API can access an accelerator device that is either local or a remote accelerator device that is located on a remote accelerator sled over a network fabric. The API may employ a send queue and a receive queue to send and receive command capsules to and from the accelerator sled.

公开(公告)号：US11184261B2

公开(公告)日：2021-11-23

申请号：US15396473

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: H04L12/26 ,  G06F16/901 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L12/24 ,  H04L12/931 ,  H04L12/947 ,  H04L29/08 ,  H04L29/06 ,  H04Q11/00 ,  H05K7/14 ,  G06F15/16 ,  G06F9/38 ,  G06F9/50 ,  H04L12/851 ,  H04L12/811 ,  H05K5/02 ,  H04W4/80 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04 ,  H04J14/00 ,  H04L12/911 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933

Abstract: Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units each linked to each other via paths of communication and the circuit switch.

公开(公告)号：US11119838B2

公开(公告)日：2021-09-14

申请号：US16572382

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Camille C. Raad

IPC: G06F11/07 ,  G09C1/00 ,  G11C29/52 ,  G11C5/04 ,  G11C29/04

Abstract: Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.

公开(公告)号：US20210248026A1

公开(公告)日：2021-08-12

申请号：US17153337

申请日：2021-01-20

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Theodros Yigzaw ,  Murugasamy Nachimuthu ,  Ashok Raj ,  Jose Vargas

IPC: G06F11/07

Abstract: Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.

公开(公告)号：US11048587B2

公开(公告)日：2021-06-29

申请号：US16292085

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/14 ,  G06F11/10

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US11016832B2

公开(公告)日：2021-05-25

申请号：US16344582

申请日：2017-11-29

Applicant: INTEL CORPORATION

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Krishna Bhuyan

IPC: G06F11/07 ,  G06F11/30 ,  H05K7/14 ,  G06F9/50 ,  G06F11/34 ,  H04Q11/00 ,  G06F16/28

Abstract: Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

公开(公告)号：US10956325B2

公开(公告)日：2021-03-23

申请号：US15375675

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mohan J. Kumar ,  Thomas Willhalm ,  Robert G. Blankenship

IPC: G06F3/06 ,  G06F12/08 ,  G06F13/00 ,  G06F12/0808 ,  G06F13/16 ,  G06F12/128 ,  G06F12/12 ,  G06F12/0868 ,  G06F12/0831

Abstract: Embodiments provide for a processor including a cache a caching agent and a processing node to decode an instruction including at least one operand specifying an address range within a distributed shared memory (DSM) and perform a flush to a first of a plurality of memory devices in the DSM at the specified address range.

公开(公告)号：US10931550B2

公开(公告)日：2021-02-23

申请号：US15656830

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy J. Nachimuthu

IPC: H04L12/26 ,  G06F16/901 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L12/24 ,  H04L12/931 ,  H04L12/947 ,  H04L29/08 ,  H04L29/06 ,  H04Q11/00 ,  H05K7/14 ,  G06F9/38 ,  G06F9/50 ,  H04L12/851 ,  H04L12/811 ,  H05K5/02 ,  H04W4/80 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04 ,  H04L12/911 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933

Abstract: Out-of-band management techniques for networking fabrics are described. In an example embodiment, an apparatus may comprise a packet-switched network interface to deconstruct a packet received via an out-of-band management network and control circuitry to execute an out-of-band management agent, and the out-of-band management agent may be operative to identify a configuration command comprised in the received packet and control an optical circuit-switched network interface based on the configuration command. Other embodiments are described and claimed.

公开(公告)号：US10756886B2

公开(公告)日：2020-08-25

申请号：US16045345

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Yadong Li ,  Michael Orr ,  Anjaneya Reddy Chagam Reddy ,  Mohan J. Kumar

IPC: G06F16/25 ,  H04L9/08 ,  G06F3/06 ,  G06F9/50 ,  H04L29/06 ,  H04L29/08 ,  G06F16/2453 ,  H04L12/861 ,  G11C8/12 ,  G11C29/02 ,  H04L12/24 ,  G06F30/34 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L12/703 ,  H04L12/743 ,  H04L12/801 ,  H04L12/803 ,  H04L12/935 ,  H04L12/931 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F16/11 ,  G06F12/0802 ,  G06F12/1045

Abstract: Technologies for load balancing a storage network include a system. The system includes circuitry to adjust routing rules in a network interface controller to deliver a packet from one of multiple uplinks to one of any physical functions, circuitry to remap, in response to a failure of a switch, a port from one physical function to another physical function, and circuitry to communicate control data between a software defined network controller and one or more agents in one or more host endpoints with a hierarchical distributed hashing table.