公开(公告)号：US20180241842A1

公开(公告)日：2018-08-23

申请号：US15435371

申请日：2017-02-17

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Andrew J. Herdrich

IPC: H04L29/08 ,  H04L12/801 ,  H04L12/927

CPC classification number: H04L67/322 ,  H04L47/18 ,  H04L47/805

Abstract: There is disclosed in an example, a fabric interface device, having: a fabric interconnect to communicatively couple to a fabric; service level agreement (SLA) input logic to receive an SLA data structure from a controller, the SLA data structure providing an end-to-end SLA for a resource flow provided by a plurality of resources, and comprising QoS metrics for the resources; and SLA output logic to propagate the QoS metrics out to the resources via the fabric interconnect.

公开(公告)号：US20180006951A1

公开(公告)日：2018-01-04

申请号：US15201394

申请日：2016-07-02

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

IPC: H04L12/803 ,  H04L29/08 ,  H04L12/26

CPC classification number: H04L43/08 ,  G06F9/505 ,  H04L43/0817 ,  H04L43/0852 ,  H04L43/0888 ,  H04L43/0894 ,  H04L47/822 ,  H04L49/505 ,  H04L67/1002 ,  H04L67/1023

Abstract: Examples may include techniques to distribute queries in a fabric of nodes configured to process the queries. A load balancing switch coupled to the nodes can receive indications of resource metrics from the nodes and can schedule and distribute the queries based on the resource metrics and network metrics identified by the switch. The switch can include programmable circuitry to receive selected resource metrics and identify selected network metrics and to distribute queries to nodes based on the metrics and distribution logic.

公开(公告)号：US20170116133A1

公开(公告)日：2017-04-27

申请号：US14921809

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/00 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/221

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

公开(公告)号：US20160283354A1

公开(公告)日：2016-09-29

申请号：US14670965

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Philip R. Lantz ,  Thomas Willhalm ,  Kirill Instrumentov ,  Karthik Kumar

IPC: G06F11/36

CPC classification number: G06F11/3688 ,  G06F11/3648

Abstract: Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.

Abstract translation: 用于软件测试的技术包括具有持久存储器的计算设备，其包括平台模拟器和要测试的应用或其他代码模块。 计算设备使用平台模拟器在测试位置生成应用程序的检查点。 计算设备从测试位置执行应用程序到终端位置，并使用平台模拟器跟踪对持久存储器的所有写入。 计算设备产生由平台模拟器模拟的计算设备的硬件规范允许的持久存储器写入的排列。 计算设备从检查点重播每个置换，模拟电源故障，然后使用平台模拟器调用用户定义的测试功能。 计算设备可以测试存储器写入的不同排列，直到应用程序使用永久存储器被验证为止。 描述和要求保护其他实施例。

公开(公告)号：US12271248B2

公开(公告)日：2025-04-08

申请号：US17358908

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Marcos E. Carranza ,  Cesar Martinez-Spessot ,  Mustafa Hajeer

IPC: G06F1/3228 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/329 ,  G06F9/50

Abstract: System and techniques for power-based adaptive hardware reliability on a device are described herein. A hardware platform is divided into multiple partitions. Here, each partition includes a hardware component with an adjustable reliability feature. The several partitions are placed into one of multiple reliability categories. A workload with a reliability requirement is obtained and executed on a partition in a reliability category that satisfies the reliability requirements. A change in operating parameters for the device is detected and the adjustable reliability feature for the partition is modified based on the change in the operating parameters of the device.

公开(公告)号：US20250086424A1

公开(公告)日：2025-03-13

申请号：US18953955

申请日：2024-11-20

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Marcos Carranza ,  Patrick Connor

IPC: G06N3/042 ,  G06N3/063

Abstract: Deployment of resources utilizing improved mixture of experts processing is described. An example of an apparatus includes one or more network ports; one or more direct memory access (DMA) engines; and circuitry for mixture of experts (MoE) processing in the network, wherein the circuitry includes at least circuitry to track routing of tokens in MoE processing, prediction circuitry to generate predictions regarding MoE processing, including predicting future token loads for MoE processing, and routing management circuitry to manage the routing of the tokens in MoE processing based at least in part on the predictions regarding the MoE processing.

公开(公告)号：US20250068457A1

公开(公告)日：2025-02-27

申请号：US18944987

申请日：2024-11-12

Applicant: Intel Corporation

Inventor： Marcos Carranza ,  Karthik Kumar ,  Mariano Ortega De Mues ,  Mateo Guzman ,  Patrick Connor ,  Cesar Martinez-Spessot

IPC: G06F9/455

Abstract: An apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (CV) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface device; access instructions to cause the portions of the set of the CV processes to be deployed on the host device and the programmable network interface device; and wherein a media processing portion of the set of the CV processes is to be deployed to the programmable circuitry, and wherein the programmable circuitry is to utilize media processing hardware circuitry hosted by the apparatus to perform the media processing portion.

公开(公告)号：US20250068438A1

公开(公告)日：2025-02-27

申请号：US18945955

申请日：2024-11-13

Applicant: Intel Corporation

Inventor： Mateo Guzman ,  Marcos Carranza ,  Daniel Biederman ,  Chihjen Chang ,  Jeremy Petsinger ,  Yadong Li ,  Mitu Aggarwal ,  Suyog Kulkarni ,  Mariano Ortega de Mues ,  Rajesh Poornachandran ,  Cesar Martinez ,  Mats Agerstam ,  Francesc Guim Bernat ,  Karthik Kumar ,  Usharani Ayyalasomayajula

IPC: G06F9/445

Abstract: Described herein are technique to enable the autonomous generation of configurations for a network environment, including but not limited to an edge network of a datacenter. Additional embodiments include prompt-based generation of network and device configurations and neural network based systems for adaptive network management.

公开(公告)号：US12223371B2

公开(公告)日：2025-02-11

申请号：US17033303

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Mark D. Tetreault

IPC: G06F9/46 ,  G06F9/54 ,  G06F9/48 ,  G06F9/50

Abstract: Systems and methods for inter-kernel communication using one or more semiconductor devices. The semi-conductor devices include a kernel. The kernel may be in an inactive state unless performing an operation. One kernel of a first device may monitor data for an event. Once an event has occurred, the kernel sends an indication to a first inter-kernel communication circuitry. The inter-kernel communication circuitry determines an activation function of a plurality of activation functions is to be generated, generates the activation function, and transmits the activation function to a second kernel of a second device to waken and perform a function using a peer-to-peer connection.

公开(公告)号：US12204396B2

公开(公告)日：2025-01-21

申请号：US17132202

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Timothy Verrall

IPC: G06F1/32 ,  G06F1/329 ,  G06F9/48 ,  G06N20/00 ,  H04L41/5003

Abstract: Various aspects of methods, systems, and use cases include coordinating actions at an edge device based on power production in a distributed edge computing environment. A method may include identifying a long-term service level agreement (SLA) for a component of an edge device, and determining a list of resources related to the component using the long-term SLA. The method may include scheduling a task for the component based on the long-term SLA, a current battery level at the edge device, a current energy harvest rate at the edge device, or an amount of power required to complete the task. A resource of the list of resources may be used to initiate the task, such as according to the scheduling.