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公开(公告)号：JPS63314032A
公开(公告)日：1988-12-22
申请号：JP15093187
申请日：1987-06-17
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To realize the construction of a satellite communication system of perfect random access system in which the collision of data is evaded, by employing a system compatible for frequency division multiplex (FDM) and code division multiplex (COM) as a communication system, and employing a pre-assign system as line allocation. CONSTITUTION:An inverse diffusion circuit 1a and a PSK demodulator 2a constitute a pilot signal reception circuit, and an inverse diffusion circuit 1b and a PSK demodulator 2b constitute a data signal reception circuit, and an inverse diffusion circuit 1c constitutes a part of a transmission timing control means. Also, when no data is transmitted from a terminal, a mode is set at a reception mode by setting the channel number of its own station at the inverse diffusion circuit 1b by a control circuit 12. In other words, the system compatible for the FDM and the CDM is employed as the communication system, and the number of channels is decided by the combination of them, and also, the channel number is set by the pre-assign system. In such a way, since it is possible to set an independent channel, and the establishment of synchronization between its own station and an opposite station based on synchronization control according to a pilot signal can be performed, the satellite communication system of perfect random access system in which the collision of the data is evaded can be realized.
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公开(公告)号：JPS63167541A
公开(公告)日：1988-07-11
申请号：JP31332086
申请日：1986-12-29
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To miniaturize the communication system by inserting a stuff word including a stuff bit, a timing error part and a stuff designation part to a prescribed timing location of a transmission data series periodically so as to digitize all processings. CONSTITUTION:An original data stored in an original clock in an FIFO memory 1 is read by a stuffing circuit 3'. A transmission data series formed by the content of the memory 1 read out by the operating clock comprising the frequency slightly higher than the frequency of the original clock is formed, and the phase error between the original clock and the operating clock is detected by a phase comparator 2. The stuff word including the stuff bit, the timing error part and the stuff designation part is inserted periodically to the prescribed position of the transmission data system based on the output of the comparator 2. A reception side circuit uses a stuff word decoding circuit 13, to extract the stuff word from the reproducing data, thereby selecting the contents to be written in the FIFO memory 11.
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公开(公告)号：JPS63161715A
公开(公告)日：1988-07-05
申请号：JP30971686
申请日：1986-12-25
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To contrive the improvement of arithmetic speed and to reduce a circuit scale by providing a basic digital filter to each of bit signals and placing the object of filter processing onto one bit data so as to constitute the titled circuit by an FIR type filter. CONSTITUTION:In M-set of basic digital filters 10-11-M, filtering is processed to each of m-order of bit signals of a data signal in M-bit binary representation, a processing result data comprising a prescribed bit number is sent to corresponding weight circuits 20-2M-1 to apply the weighting of 2 and sent to an adder. Then the adder takes the sum of outputs of M-set of weighting circuits and gives an output. Since the object of filtering processing of the basic digital filter is one-bit data, in constituting the filter by a definite impulse response (FIR) type filter, the circuit is constituted without using a complicated multilayer, the circuit scale is reduced and the operating speed is improved.
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公开(公告)号：JPS6278902A
公开(公告)日：1987-04-11
申请号：JP21883285
申请日：1985-10-01
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To obtain a necessary high output from a small-scale high power amplifier(HPA) and to realize an unmanned earth station by by receiving the output signal of the 1st detector and the output signal of the 2nd detector and generating a voltage corresponding to the amplitude difference between both signals, and applying it as a control signal to a variable attenuator. CONSTITUTION:The vector modulators(V.M.) consisting of two components, i.e. a variable attenuator 7 and a phase shifter 9 are brought under negative feedback control and then one fine part signal 104 of the output of an HPA 1 which is led out by a coupler 2 is controlled to the same amplitude and phase with the output of a delay device 3. The delay device 3 compensates signal delay caused in the V.M. and HPA 1, but the V.M. and HPA 1 normally have a wide band, so the quantity of the delay is small. Thus, an output signal 103 becomes invariably in phase with an input signal 101 and the HPA 1 is linearized. For the purpose, the amplitudes and phases of the input and output signals of the HPA are detected directly, and distortion control is performed through a negative feedback loop on the basis of the result, so that accurate distortion corrections are made.
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公开(公告)号：JPS6259432A
公开(公告)日：1987-03-16
申请号：JP19859685
申请日：1985-09-10
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To attain miniaturization and stable conversion by converting a frequency division multiplex signal into a complex number signal, applying frequency conversion and digitizing, using a chirp signal generator and a chirp filter to convert the result into a time division multiplex signal or to apply inverse conversion. CONSTITUTION:An input signal is inputted to mixers 4, 5, where the signal is converted into a complex number signal and fed to A/D converters 10, 11 via LPFs 8, 9. An output of the chirp signal generator 2 comprising M-set of digital sub filters and an A/D conversion value are fed to a multiplier 12 to a minimum square number M larger than the required total number of channels. The output of the generator 2 is multiplex by a multiplier 13 with a minimum square value M larger than the required total number of channels via a chirp filter 1 comprising M sets of digital sub filters. The multiplicand is subject to 2-series analog signals by D/A converters 14, 15 and the 2-series analog signal is a synthesized signal 16 by the inverse conversion. Thus, the conversion circuit is miniaturized and the conversion with stable characteristic is attained.
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Patent Agency Ranking
公开(公告)号：JPS61140226A
公开(公告)日：1986-06-27
申请号：JP26253084
申请日：1984-12-12
Applicant: Nec Corp
Inventor： ICHIYOSHI OSAMU
CPC classification number: H04B1/10
Abstract: PURPOSE:To improve the ratio of an output signal and an interference wave electric power by synthesizing desired wave with the output of the first signal synthesizing device and the second signal synthesizing device, detecting the correlation with a signal that passes an adaptive filter, controlling the frequency characteristic and minimizing an output voltage. CONSTITUTION:A code X indicates a signal on a main receiving circuit and codes Y1, Y2...Yn indicate signals on an auxiliary receiving circuit. The circuit consists of a signal synthesizing device 51 having n+1 input terminals, adaptive filters 52-1, 52-2...52-n, a desired wave signal suppressing circuit 53 that generates an estimated interference wave signal Ex by suppressing a desired wave signal from the output Ex of the signal composing device 51, correlation detection controlling circuits 54-1, 54-2...54-n that make the correlation detection of output Ex of desired wave signal suppressing signal 53 and the respective output of adaptive filters 52-1-52-n and generate controlling signals that control corresponding adaptive filters, an estimated desired wave generating circuit 54 that generates estimated desired wave basing on the output Ex of the signal composing device 51, a delaying device 56, a signal composing device 57, a signal composing device 57, a delaying device 58, a correlation detector 59, a sample holder 63, a low pass filter 61, a DC amplifier 62 etc.
Abstract translation: 目的：通过将期望波与第一信号合成装置和第二信号合成装置的输出合成来提高输出信号和干扰波电力的比例，检测与通过自适应滤波器的信号的相关性， 频率特性并使输出电压最小化。 构成：代码X表示主接收电路上的信号，代码Y1，Y2 ... Yn表示辅助接收电路上的信号。 电路由具有n + 1个输入端子的信号合成装置51，自适应滤波器52-1,52-2 ... 52-n构成，所希望的波信号抑制电路53通过抑制 信号合成装置51的输出Ex，相关检测控制电路54-1,54-2 ... 54-n的期望波信号，对相关检波控制电路54-1,54-2 ... 54-n进行相关检测， 自适应滤波器52-1-52-n，并产生控制对应的自适应滤波器的控制信号，估计的期望波发生电路54，其产生基于信号合成装置51的输出Ex的估计期望波，延迟装置56， 信号合成装置57，信号合成装置57，延迟装置58，相关检测器59，样品保持器63，低通滤波器61，直流放大器62等。
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公开(公告)号：JP2001320684A
公开(公告)日：2001-11-16
申请号：JP2000140669
申请日：2000-05-12
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04B7/15 , H04B7/155 , H04B7/185 , H04L12/18 , H04M3/56 , H04M11/00 , H04N5/44 , H04N7/15 , H04N7/16
Abstract: PROBLEM TO BE SOLVED: To provide a satellite conference system by which many participants can securely and inexpensively hold a conference in an immediate system. SOLUTION: Utterance contents of an utterer taking part in a conference are broadcast through a communication satellite to participants each having a satellite communication terminal provided with a means receiving a signal from the communication satellite, and a conference center connected to a satellite earth station making satellite communication with the communication satellite is provided with a return path communication means that receives an utterance right request signal from conference participants and an utterance signal of a participant to which an utterance right is given, and ground communication using a ground communication network is made to participants each having a satellite communication terminal without a transmission means to the communication satellite.
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公开(公告)号：JP2001320480A
公开(公告)日：2001-11-16
申请号：JP2000139117
申请日：2000-05-11
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PROBLEM TO BE SOLVED: To realize a computer communication network open to the public with a simple network configuration where the management of information is secured. SOLUTION: The computer communication network is provided with user terminals 1 that are directly connected to a public line having an exchange for communication and with an address server 3 for conversion service between an address name and an address number and users can attain interconnection by using an easily understandable name.
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公开(公告)号：JP2001308768A
公开(公告)日：2001-11-02
申请号：JP2000116389
申请日：2000-04-18
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04B7/185 , H04B7/204 , H04H20/00 , H04H20/74 , H04L12/18 , H04L12/58 , H04N5/44 , H04N5/445 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/173 , H04N7/20 , H04H1/00 , H04L12/54
Abstract: PROBLEM TO BE SOLVED: To provide a data distribution system to provide a variety of materials in a broadcast mode to a user having a satellite communication terminal capable of receiving a signal from a communication satellite. SOLUTION: The system has a data (distribution) center connected to a satellite earth station in order to transmit the broadcast signal to the communication satellite, and the data center publishes contents of accumulated information on an Internet homepage(HP) for presenting them to the user for retrieval. The user determine data to be obtained by retrieving them on the HP, and transmit a request signal to the data center via the Internet on the ground or the communication satellite. The data center returns a reservation signal including a group address and a distribution estimated time to the demander via the satellite. A user terminal receives data to which the group address given to a reserved time of day is attached, decodes them by a key separately given from the data center, then accumulate them in a memory.
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公开(公告)号：JPH08242263A
公开(公告)日：1996-09-17
申请号：JP4561595
申请日：1995-03-06
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE: To obtain a high power transmitter enabling linear amplification of wide band signals. CONSTITUTION: In the transmitter where carrier waves are modulated in a D/A converter 41 and a QAM(quadrature amplitude modulation) modulator 42, the waves are amplified in a high power amplifier 1 and the waves are transmitted after the amplitude and phases of transmission signals x and y are adjusted so that the non-linear characteristic of a poststage circuit may be compensated in a complex multiplier 22, the control of the complex multiplier 22 is performed for two systems. A complex memory 25 storing control data is used and the one system is controlled by reading control value data α, βof the number designated by the amplitude of the transmission signal from the memory 25. For the other system, amplitude and a phase error are detected from the transmission signal and the transmission output in an error detector 31 and a control update miry 30, the corrected values α", β" of control value data are calculated and the storage value of control valued data is updated.
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