Abstract:
An oscillator having a first phase-shifting network, an inverting amplifier and a second phase-shifting network comprising two impedances; one of the impedances is externally adjustable and determines the frequency of the oscillator signal. A total phase shift of 180* is achieved by means of the first phase-shifting network which provides a phase shift of substantially 90* in a frequency independent manner and by the second phase-shifting network which provides an additional phase shift of substantially 90* in a frequency-dependent manner.
Abstract:
조정 가능한 공진 회로(102)는 제1 커패시터의 제1 전극과 제2 전극 및 제2 커패시터의 제1 전극과 제2 전극 사이에 정합 커패시턴스를 제공하는 제1 커패시터들(104, 108, 216, 228, 232) 및 제2 커패시터들(106, 110, 218, 230, 234)를 포함한다. 딥 웰 장치는 기판(324)의 제2 웰(322, 328) 내에 배치된 제1 웰(320, 326)을 포함한다. 제1 커패시터 및 제2 커패시터 각각은 제1 웰 상에 배치될 수 있다. 제1 트랜지스터의 2개의 채널 전극(120, 130)은 제1 커패시터의 제2 전극(114, 304) 및 제2 커패시터의 제2 전극(118, 308)에 각각 결합된다. 제2 트랜지스터의 2개의 채널 전극(122, 132)은 제1 커패시터의 제2 전극 및 그라운드에 각각 결합된다. 제3 트랜지스터의 2개의 채널 전극(124, 134)은 제2 커패시터의 제2 전극 및 그라운드에 각각 결합된다. 제1 트랜지스터, 제2 트랜지스터, 및 제3 트랜지스터의 게이트 전극들(226, 314)은 조정 신호(126, 136)에 응답할 수 있고, 인덕터(144, 202)는 제1 커패시터 및 제2 커패시터의 제1 전극들(112, 116, 302, 306) 사이에 결합될 수 있다.
Abstract:
본 발명은 에프엠 변조기에 관한 것으로, 변환하고자 하는 전압(Vin), 기준 전압(Vref) 및 중심 주파수와 변조도를 조정하기 위한 조정 전압(V CT )을 입력받아, 입력된 조정 전압을 통해서 중심 주파수와 변조도를 동시에 조정할 수 있는 제어 전류(iCT)를 발생시켜 출력하는 전압-전류 변환 수단과, 상기 전압-전류변환 수단으로부터 출력되는 제어 전류를 입력 받아, 변조된 주파수를 발진하는 주파수 변조 수단로 구성되었으며, 중심 주파수를 조정하고 에프엠 변조량을 조정하는 데에 있어서, 하나의 조정 전압(V CT )에 의해서 단지 중심 주파수를 조정하는 것만으로 변조도도 동시에 조정할 수 있도록 한 에프엠 변조기에 관한 것이다.
Abstract:
The circuit improves frequency stability, and extends a variable frequency range by a negative feedback and negative resistance circuit. The circuit includes a 1st condenser (C1) and negative resistance circuit, a 2nd condenser (C2) which connects a 2nd gm amplifier output terminal to ground. The negative resistance circuit (12) between 1st gm amplifier (10) and 2nd gm amplifier (11), improves frequency stability, adjusts a selectivity, and specifies oscillating conditions. The gm amplifier varies a gm value by voltage control signal (Vctl), and varies an oscillating frequency, and specifies an oscillating frequency.
Abstract:
An oscillator circuit includes an amplifier including a first transconductance amplifier and a second transconductance amplifier; and a resonator including a capacitor element and an inductor element. The capacitor element includes a first capacitor and a second capacitor, the inductor element includes a tapped inductor, the tapped inductor includes a first segment of inductor and a second segment of inductor, and the first segment of inductor and the second segment of inductor are coupled using the first capacitor. The first segment of inductor includes a first terminal and a second terminal coupled to an input terminal and an output terminal of the first transconductance amplifier respectively. The second segment of inductor includes a third terminal and a fourth terminal coupled to an input terminal and an output terminal of the second transconductance amplifier, respectively.
Abstract:
A self-oscillation circuit includes an oscillating unit, an amplifying unit, and a resonator. The oscillating unit is configured to self-oscillate. The amplifying unit is configured to amplify a frequency signal oscillated at the oscillating unit and to feed back the amplified frequency signal to the oscillating unit. The resonator is disposed in an oscillation loop that includes the oscillating unit and the amplifying unit. The resonator has a resonant frequency near an oscillation frequency of the oscillating unit and has a higher Q-value than a Q-value of the oscillating unit.
Abstract:
A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors.
Abstract:
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.