公开(公告)号：US20170279458A1

公开(公告)日：2017-09-28

申请号：US15504150

申请日：2015-09-25

Applicant: Continental Teves AG & Co.oHG

Inventor： Heinrich Acker

IPC: H03M1/06 ,  H03M1/60 ,  H03M1/00 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/0626 ,  H03M1/002 ,  H03M1/0614 ,  H03M1/1009 ,  H03M1/124 ,  H03M1/201 ,  H03M1/60

Abstract: A device for digitizing an analogue signal, wherein a distortion signal outlet of a distortion signal generator is only coupled to an analogue digital converter by passive components.

公开(公告)号：US09667267B2

公开(公告)日：2017-05-30

申请号：US15121381

申请日：2015-01-28

Applicant: China Electronic Technology Corporation, 24th Research Institute

Inventor： Yan Wang ,  Gang-Yi Hu ,  Tao Liu ,  Yu-Xin Wang ,  Jian-An Wang ,  Dong-Bing Fu ,  Ting Li ,  Guang-Bing Chen

IPC: H03M1/20 ,  H03M1/10 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06 ,  H03M1/74

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/1009 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/742

Abstract: A dither circuit for high-resolution analog-to-digital converters (ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.

公开(公告)号：US20160056762A1

公开(公告)日：2016-02-25

申请号：US14831091

申请日：2015-08-20

Applicant: Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03B5/12

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。

公开(公告)号：US09054727B2

公开(公告)日：2015-06-09

申请号：US14162559

申请日：2014-01-23

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/20 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract translation: 一种模数转换器（ADC）系统和方法。 根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。 控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。 呈现了几个实施例。

公开(公告)号：US20140320324A1

公开(公告)日：2014-10-30

申请号：US14258102

申请日：2014-04-22

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： David CANARD ,  Julien DELORME

IPC: H03M1/20 ,  H03L7/093

CPC classification number: H03M1/201 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/18

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract translation: 描述了使用基于时间数字转换器TDC（20）的基于延迟元件的布置的时间 - 数字转换方案，其中抖动内置在数字域中并被引入模拟域中作为电源的调制 电压（TDC电源）提供TDC的延迟元件，每个延迟元件具有表现出对其电源电压的依赖性的传播延迟。

公开(公告)号：US08823565B2

公开(公告)日：2014-09-02

申请号：US13940819

申请日：2013-07-12

Applicant: Renesas Electronics Corporation

Inventor： Keisuke Kimura ,  Tatsuji Matsuura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

IPC: H03M1/20

CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

公开(公告)号：US20140132432A1

公开(公告)日：2014-05-15

申请号：US14162572

申请日：2014-01-23

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jesper STEENSGAARD-MADSEN

IPC: H03M1/20

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

公开(公告)号：US08519878B2

公开(公告)日：2013-08-27

申请号：US13170155

申请日：2011-06-27

Applicant: Henrik Tholstrup Jensen ,  Jianhua Gan ,  Seema Anand ,  Aminghasem Safarian

Inventor： Henrik Tholstrup Jensen ,  Jianhua Gan ,  Seema Anand ,  Aminghasem Safarian

IPC: H03M1/12

CPC classification number: H03M1/201 ,  H03M3/332 ,  H03M3/396 ,  H03M3/406 ,  H03M3/456

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency bands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract translation: 技术和设备在两个或多个信号频率或频带上提供模数转换，并可用于在各种电路中构建多模式模数转换器，包括用于无线通信和无线电广播环境的接收机和收发器。 可以配置基于所述技术的可调节模数转换器，以调整电路参数，以适应不同信号频率或频段的不同输入信号的技术规格，例如无线电中的FM，HD-无线电和DAB无线电信号 接收机应用。

公开(公告)号：US20130015988A1

公开(公告)日：2013-01-17

申请号：US13192056

申请日：2011-07-27

Applicant: Bob Verbruggen ,  Jan Craninckx

Inventor： Bob Verbruggen ,  Jan Craninckx

IPC: H03M1/34 ,  H03M1/12

CPC classification number: H03M1/201 ,  H03M1/04 ,  H03M1/164 ,  H03M1/44 ,  H03M1/46

Abstract: An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described. The A/D converter circuit includes: a first converter stage configured for receiving the analog input signal and for generating a first set of conversion bits, a first completion signal and a residual analog output signal representing the difference between the analog input signal and a signal represented by said first set of conversion bits, a second converter stage comprising a clock generation circuit arranged for receiving the first completion signal and for generating a clock signal, a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions, a digital processing stage configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits, means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits.

Abstract translation: 描述了用于接收模拟输入信号并输出​​所述模拟输入信号的数字表示的模拟（A / D）转换器电路。 A / D转换器电路包括：第一转换器级，被配置为接收模拟输入信号并产生第一组转换位，第一完成信号和表示模拟输入信号与信号之间的差的残留模拟输出信号 由所述第一组转换位表示的第二转换器级，包括布置成用于接收第一完成信号并用于产生时钟信号的时钟产生电路，多个比较器被配置为用于接收残留模拟输出信号和公共参考 电压，所述多个比较器被布置成被时钟信号激活并用于输出多个比较器判定;数字处理级，被配置用于接收多个比较器判决并用于产生第二组转换位，用于产生数字 通过组合第一个a来表示模拟输入信号 第二组转换位。

公开(公告)号：US08223049B2

公开(公告)日：2012-07-17

申请号：US12959317

申请日：2010-12-02

Applicant: Fredrik Larsen ,  Frode Milch Pedersen ,  Jan Rune Herheim ,  Ronan Barzic

Inventor： Fredrik Larsen ,  Frode Milch Pedersen ,  Jan Rune Herheim ,  Ronan Barzic

IPC: H03M1/00

CPC classification number: H03M1/1038 ,  H03M1/201

Abstract: A low-cost charge injection mechanism may enable oversampling to be used on low frequency signals by injecting dither noise into the ADC input. The dither noise can reduce the quantization noise allowing even direct current (DC) signals to be oversampled correctly. A low-cost charge injection mechanism can also be used to improve the ENOB by characterizing the ADC and digitally correcting the converted signal for non-linearity errors such as INL. Reducing INL errors may also allow a higher degree of oversampling to be used to further improve the ENOB.

Abstract translation: 低成本电荷注入机制可以通过将抖动噪声注入到ADC输入中来实现对低频信号的过采样。 抖动噪声可以降低量化噪声，从而允许正确的电流（DC）信号被过采样。 还可以使用低成本电荷注入机制来改善ENOB，通过对ADC进行特征化并对非线性误差（如INL）进行数字校正转换的信号。 降低INL误差还可能允许使用更高程度的过采样来进一步改善ENOB。