公开(公告)号：US20140312943A1

公开(公告)日：2014-10-23

申请号：US14256015

申请日：2014-04-18

Applicant: Asahi Kasei Microdevices Corporation

Inventor： David CANARD

IPC: H03L7/095

CPC classification number: H03L7/095 ,  H03L7/1075 ,  H03L2207/06

Abstract: A phase-locked loop device is configured to manage a transition from a relaxation-oscillation mode to a random noise operation mode. It is designed for progressively reducing proportional and integral coefficients that are implemented in a loop filter of the PLL device. Recovering the last values formerly used for the proportional and integral coefficients is also provided, in case the PLL lock state is lost. Such transition management may be combined with using a voltage-controlled oscillator within the PLL device, which has several control inputs.

Abstract translation: 锁相环装置被配置为管理从松弛振荡模式到随机噪声操作模式的转变。 它被设计用于逐渐减少在PLL器件的环路滤波器中实现的比例和积分系数。 在PLL锁定状态丢失的情况下，还提供恢复以前用于比例和积分系数的最后一个值。 这种转换管理可以与使用具有若干控制输入的PLL器件内的压控振荡器组合。

公开(公告)号：US20140320324A1

公开(公告)日：2014-10-30

申请号：US14258102

申请日：2014-04-22

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： David CANARD ,  Julien DELORME

IPC: H03M1/20 ,  H03L7/093

CPC classification number: H03M1/201 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/18

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract translation: 描述了使用基于时间数字转换器TDC（20）的基于延迟元件的布置的时间 - 数字转换方案，其中抖动内置在数字域中并被引入模拟域中作为电源的调制 电压（TDC电源）提供TDC的延迟元件，每个延迟元件具有表现出对其电源电压的依赖性的传播延迟。

公开(公告)号：US20140340161A1

公开(公告)日：2014-11-20

申请号：US14273721

申请日：2014-05-09

Applicant: Asahi Kasei Microdevices Corporation

Inventor： David CANARD ,  Sebastien CHARPENTIER ,  Matthieu LECUYER

IPC: H03L7/099

CPC classification number: H03L7/0992 ,  H03L7/093 ,  H03L7/099 ,  H03L7/103 ,  H03L7/1976 ,  H03L2207/06

Abstract: A digital phase-locked loop (PLL) device includes a digital loop filter which is provided with both a VCO-loop output and a DCO-loop output. The VCO-loop output is connected to an analog input of a multiband voltage-controlled oscillator (VCO) module for allowing usual operation of the PLL with a direct voltage acting as feedback parameter. The DCO-loop output is connected to a digital control input of the multiband VCO module for allowing automatic frequency range selection. A code value which is produced by the digital loop filter acts as feedback parameter during the frequency range selection. Rapid and precise range selection can thus be performed.

Abstract translation: 数字锁相环（PLL）器件包括一个数字环路滤波器，同时具有VCO环路输出和DCO环路输出。 VCO环路输出连接到多频段压控振荡器（VCO）模块的模拟输入，用于允许PLL作为反馈参数的直流电压的常规操作。 DCO环路输出连接到多频段VCO模块的数字控制输入，用于允许自动频率范围选择。 由数字环路滤波器产生的码值在频率范围选择期间作为反馈参数。 因此可以进行快速精确的范围选择。