公开(公告)号：EP2784823B1

公开(公告)日：2018-05-23

申请号：EP14168446.4

申请日：2008-12-19

Applicant: Asahi Kasei EMD Corporation

Inventor： Koricic, Marko ,  Suligoj, Tomislav ,  Mochizuki, Hidenori ,  Morita, Soichi

IPC: H01L29/735 ,  H01L21/331 ,  H01L21/8249 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L27/0623 ,  H01L21/2257 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/8249 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/1045 ,  H01L29/6625 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/735

Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.

公开(公告)号：EP2224478B1

公开(公告)日：2018-01-24

申请号：EP08865744.0

申请日：2008-12-19

Applicant: Asahi Kasei EMD Corporation

Inventor： KORICIC, Marko ,  SULIGOJ, Tomislav ,  MOCHIZUKI, Hidenori ,  MORITA, Soichi

IPC: H01L29/735 ,  H01L21/331 ,  H01L21/8249 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/225

CPC classification number: H01L27/0623 ,  H01L21/2257 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/8249 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/1045 ,  H01L29/6625 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/735

Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.

公开(公告)号：EP1788351B1

公开(公告)日：2017-05-03

申请号：EP05782322.1

申请日：2005-09-08

Applicant: MURATA MANUFACTURING CO., LTD. ,  Asahi Kasei EMD Corporation

Inventor： MORI, Akira ,  NAGAI, Iku ,  SAWADA, Kazushige ,  NARITA, Makoto

IPC: G01C19/56 ,  G01C19/5776

CPC classification number: G01C19/5776

公开(公告)号：EP2131398B1

公开(公告)日：2015-05-20

申请号：EP08738698.3

申请日：2008-03-21

Applicant: Asahi Kasei EMD Corporation

Inventor： SHIBATA, Yoshihiko ,  MIYAHARA, Masatoshi

IPC: H01L29/26 ,  C30B23/02 ,  C30B29/40 ,  C30B25/18 ,  H01L21/20 ,  H01L29/20 ,  H01L43/06 ,  H01L43/08

CPC classification number: H01L29/20 ,  C30B23/025 ,  C30B25/18 ,  C30B29/40 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/0254 ,  H01L21/02549 ,  H01L29/201 ,  H01L29/267 ,  H01L43/065

公开(公告)号：EP2784823A3

公开(公告)日：2015-02-25

申请号：EP14168446.4

申请日：2008-12-19

Applicant: Asahi Kasei EMD Corporation

Inventor： Koricic, Marko ,  Suligoj, Tomislav ,  Mochizuki, Hidenori ,  Morita, Soichi

IPC: H01L29/735 ,  H01L21/331 ,  H01L21/8249 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0623 ,  H01L21/2257 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/8249 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/1045 ,  H01L29/6625 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/735

Abstract: A semiconductor device in which a lateral bipolar transistor and a CMOS transistor are hybrid-integrated, and the lateral bipolar transistor includes an open region opened in a device isolating oxide film surrounding an active region; a polysilicon film formed on the open region; and a protective film covering at least a part of a peripheral surface of the active region exposed by opening the open region in the device isolating oxide film, wherein the polysilicon film has such a thickness as to expose the active region out of the polysilicon film, and the protective film is a film for preventing the active region from being etched when the polysilicon film is etched to the thickness.

公开(公告)号：EP2019488B1

公开(公告)日：2014-12-24

申请号：EP07743381.1

申请日：2007-05-15

Applicant: Asahi Kasei EMD Corporation

Inventor： KAIHO, Toshio ,  MACHIDA, Junichi

IPC: H03K17/687 ,  H03K5/06 ,  H03K17/284 ,  H03K7/08

CPC classification number: H03F3/387 ,  H03F1/3211 ,  H03F1/34 ,  H03F3/2173 ,  H03F3/45475 ,  H03F2200/351 ,  H03F2203/45138 ,  H03F2203/45526 ,  H03K5/06 ,  H03K7/08 ,  H03K17/284

公开(公告)号：EP2023398B1

公开(公告)日：2014-10-22

申请号：EP08019935.9

申请日：2004-09-09

Applicant: Asahi Kasei EMD Corporation

Inventor： Ueno, Koichiro ,  Kuze, Naohiro ,  Moriyasu, Yoshitaka ,  Nagase, Kazuhiro

IPC: H01L31/0304 ,  H01L31/0203 ,  H01L27/144

CPC classification number: H01L31/035236 ,  B82Y20/00 ,  G01J1/02 ,  G01J1/0204 ,  G01J5/02 ,  G01J5/0215 ,  G01J5/04 ,  G01J5/045 ,  G01J5/20 ,  G01J2001/0276 ,  H01L31/1035 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An infrared sensor IC and an infrared sensor, which are extremely small and are not easily affected by electromagnetic noise and thermal fluctuation, and a manufacturing method thereof are provided. A compound semiconductor that has a small device resistance and a large electron mobility is used for a sensor (2), and then, the compound semiconductor sensor (2) and an integrated circuit (3), which processes an electrical signal output by the compound semiconductor sensor (2) and performs an operation, are arranged in a single package using hybrid formation. In this manner, an infrared sensor IC that can be operated at room temperature can be provided by a microminiature and simple package that is not conventionally produced.

公开(公告)号：EP2753154A1

公开(公告)日：2014-07-09

申请号：EP11871785.9

申请日：2011-08-30

Applicant: EMD Corporation

Inventor： SETSUHARA, Yuichi ,  EBE, Akinori

IPC: H05H1/46 ,  C23C16/44 ,  C23C16/509 ,  H01L21/205 ,  H01L21/3065

CPC classification number: H01J37/32651 ,  C23C14/358 ,  C23C16/509 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/3211 ,  H01J2237/0266 ,  H05H1/46 ,  H05H2001/4667

Abstract: Provided is a radio-frequency antenna with which the blocking or weakening of a radio-frequency induction electric field will not occur even if a thin-film material deposits on the antenna surface. A radio-frequency antenna 10 includes a linear antenna conductor 13, a dielectric protective pipe 14 provided around the antenna conductor 13, and a deposit shield 15 provided around the protective pipe 14, the deposit shield 15 covering at least one portion of the protective pipe 14 and having at least one opening 153 on any line extending along the length of the antenna conductor 13. Although the thin-film material adheres to the surfaces of the protective pipe and the deposit shield, the deposited substance has at least one discontinuous portion in the longitudinal direction of the antenna conductor. Therefore, in the case where the thin-film material is electrically conductive, the blocking of the radio-frequency induction electric field is prevented. In the case where the thin-film material is not electrically conductive, an attenuation in the intensity of the radio-frequency induction electric field is suppressed.

Abstract translation: 提供一种射频天线，即使薄膜材料沉积在天线表面上也不会发生射频感应电场的阻塞或弱化。 射频天线10包括线状天线导体13，设置在天线导体13周围的介质保护管14和设置在保护管14周围的沉积屏蔽15，沉积屏蔽15覆盖保护管的至少一部分 14，并且在沿着天线导体13的长度延伸的任何线上具有至少一个开口153.尽管薄膜材料粘附到保护管和沉积屏蔽的表面上，但沉积物质具有至少一个不连续部分 天线导体的纵向。 因此，在薄膜材料导电的情况下，防止了射频感应电场的阻塞。 在薄膜材料不导电的情况下，抑制了射频感应电场强度的衰减。

公开(公告)号：EP2615889A1

公开(公告)日：2013-07-17

申请号：EP11823665.2

申请日：2011-09-09

Applicant: EMD Corporation

Inventor： SETSUHARA, Yuichi ,  EBE, Akinori

IPC: H05H1/46 ,  C23C16/509 ,  H01L21/205 ,  H01L21/3065

CPC classification number: H05H1/46 ,  C23C16/507 ,  H01J37/321 ,  H01J37/3211 ,  H01J37/32119 ,  H01J37/32477 ,  H05H2001/4667

Abstract: The present invention provides a plasma processing device which can generate plasma with a higher density than that in an external antenna type, and can prevent the impurities from being mixed into an object to be processed and can prevent particles from being generated, which are problems that occur in an internal antenna type. The plasma processing device according to the present invention has: a metallic vacuum chamber 11; an antenna-placing section 14 in which a radio-frequency antenna 18 is placed inside a through-hole (hollow space) provided in an upper wall 112 of the vacuum chamber 11; and a dielectric separating plate 15 covering the entire inner surface 1121 of the upper wall 112. In this plasma processing device, the entire inner surface 1121 side of the upper wall 112 is covered with the separating plate 15 so that surfaces in different level otherwise formed when a smaller separating plate is used is not formed between the inner surface 1121 and the separating plate 15. Therefore, the generation of particles caused by the formation of adhered materials on the surfaces in different level is prevented.

Abstract translation: 本发明提供一种等离子体处理装置，其能够生成比外部天线型的等离子体的密度更高的等离子体，并且能够防止杂质混入到被处理物中，能够防止产生粒子， 发生在内部天线类型中。 根据本发明的等离子体处理装置具有：金属真空室11; 天线放置部分14，其中高频天线18放置在设置在真空室11的上壁112中的通孔（中空空间）内; 以及覆盖上壁112的整个内表面1121的电介质分离板15.在该等离子体处理装置中，上壁112的整个内表面1121侧被分离板15覆盖，使得不同水平面 当在内表面1121和分隔板15之间不使用较小的分隔板时，因此防止了由于在不同水平面上形成粘附材料而产生的颗粒的产生。

公开(公告)号：EP2557430A1

公开(公告)日：2013-02-13

申请号：EP12183468.3

申请日：2007-03-28

Applicant: Asahi Kasei EMD Corporation

Inventor： Kataoka, Makoto ,  Kakuta, Katsumi ,  Yamagata, Yo ,  Kanayama, Yuichi

IPC: G01R33/07 ,  H01L43/06 ,  G01R33/00

CPC classification number: G01R33/07 ,  G01R33/0011 ,  H01L27/22 ,  H01L43/06

Abstract: The present invention relates to a magnetic sensor with which magnetic characteristics are made extremely stable by consideration of an area of contact of a base layer of a magnetic substance and a semiconductor substrate. On a semiconductor substrate (111) a plurality of Hall elements (112a, 112b) are embedded so as to be coplanar to a top surface of the semiconductor substrate while being mutually spaced apart by a predetermined distance, and above the Hall elements and the semiconductor substrate, a base layer (114), having coefficient of thermal expansion differing from that of the Hall elements and partially covers a region of each Hall elements, is formed via a protective layer (113), and a magnetic flux concentrator (115), having an area larger than the base layer and with magnetic amplification, is formed on the base layer. An area of contact of the base layer of the magnetic substance and the semiconductor substrate is made small to lessen the generation of an offset voltage.

Abstract translation: 磁传感器技术领域本发明涉及考虑到磁性物质的基底层与半导体基板的接触面积而使磁特性非常稳定的磁传感器。 在半导体衬底（111）上嵌入多个霍尔元件（112a，112b），以便与半导体衬底的顶表面共面一个预定距离相互间隔开，并且在霍尔元件和半导体 通过保护层（113）和磁通集中器（115）形成具有与霍尔元件的热膨胀系数不同的部分的基底层（114），并部分地覆盖每个霍尔元件的区域， 在基底层上形成具有大于基底层并且具有磁放大的面积的区域。 使磁性物质的基底层与半导体基板的接触面积小，以减少偏移电压的产生。