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    Converging time reduction method and device
    151.
    发明专利
    Converging time reduction method and device 审中-公开
    收敛时间减少方法和装置

    公开(公告)号：JP2000077979A

    公开(公告)日：2000-03-14

    申请号：JP23850799

    申请日：1999-08-25

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

    Inventor： NGUYEN THI N

    IPC: H03H17/00 ,  H03H21/00 ,  H04B3/06

    CPC classification number: H03H21/0012

    Abstract: PROBLEM TO BE SOLVED: To provide a method/device which can reduce the converging time of a digital filter while maintaining its accuracy.
    SOLUTION: When a digital filter is initially run, the coefficients of the filter are adjusted to decrease the output errors of the filter. If the adjusted filter coefficients satisfy the selected error levels, these coefficients are stored in a memory and also the digital filter filters data. When the digital filter is run, the stored coefficients are loaded into the filter and also many repetitive operations are made to run to adjust the coefficients. Then it's decided whether the adjusted coefficients satisfy the threshold that can decide that an error level is equal to the selected one. If the coefficients satisfy the threshold, these coefficients are stored in the memory and also the digital filter is used to filter the data.
    COPYRIGHT: (C)2000,JPO

    Abstract translation: 要解决的问题：提供一种能够在保持其精度的同时降低数字滤波器的会聚时间的方法/装置。 解决方案：当数字滤波器初始运行时，调整滤波器的系数以减小滤波器的输出误差。 如果调整后的滤波器系数满足选择的误差电平，则这些系数存储在存储器中，并且数字滤波器也对数据进行滤波。 当数字滤波器运行时，存储的系数被加载到滤波器中，并且进行许多重复操作以调整系数。 然后决定调整后的系数是否满足可以决定错误级别等于所选择的阈值的阈值。 如果系数满足阈值，则这些系数存储在存储器中，并且使用数字滤波器来过滤数据。

    In-line measurement for obtaining full wafer map of uniformity and surface charge
    154.
    发明专利
    In-line measurement for obtaining full wafer map of uniformity and surface charge 审中-公开
    用于获取均匀和表面充电的全幅图的在线测量

    公开(公告)号：JP2014060395A

    公开(公告)日：2014-04-03

    申请号：JP2013183545

    申请日：2013-09-05

    Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc.

    Inventor： ZHANG JOHN H

    IPC: H01L21/66 ,  G01R29/24 ,  H01L21/02

    CPC classification number: H01L22/12 ,  B24B37/005 ,  B24B37/04 ,  B24B49/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide an improved apparatus and method for performing measurement of a wafer.SOLUTION: The apparatus may include a substrate with a plurality of microprobes. A plurality of light sources may direct light onto each of the microprobes. Light reflected from the microprobes may be detected by a plurality of photodetectors, thereby detection signals each of which is associated with one of the microprobes are generated. A controller may send a driving signal to each of the plurality of microprobes, and may determine a height distribution and a surface charge distribution of the wafer on the basis of the detection signals.

    Abstract translation: 要解决的问题：提供一种用于进行晶片测量的改进的装置和方法。解决方案：该装置可以包括具有多个微探针的基板。 多个光源可以将光引导到每个微探针上。 可以由多个光电检测器检测从微探针反射的光，从而产生与微探针之一相关联的检测信号。 控制器可以向多个微探针中的每一个发送驱动信号，并且可以基于检测信号来确定晶片的高度分布和表面电荷分布。

    Electronic apparatus including shallow trench isolation (sti) region having bottom nitride liner and top oxide liner, and associated method
    155.
    发明专利
    Electronic apparatus including shallow trench isolation (sti) region having bottom nitride liner and top oxide liner, and associated method 有权
    电子设备，包括具有底部氮化物衬里和顶部氧化物衬里的浅层隔离（STI）区域，以及相关方法

    公开(公告)号：JP2014042020A

    公开(公告)日：2014-03-06

    申请号：JP2013164180

    申请日：2013-08-07

    Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc.

    Inventor： LIU QING ,  NICOLAS LOUBET ,  PRASANNA KHARE

    IPC: H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L21/76283 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76264

    Abstract: PROBLEM TO BE SOLVED: To provide an electronic apparatus capable of improving interface properties between a shallow trench isolation (STI) region and a corresponding semiconductor device, and a method for manufacturing the same.SOLUTION: An electronic apparatus can comprise a substrate, a buried type oxide (BOX) layer on the substrate, at least one of semiconductor device on the BOX layer, and at least one of STI region adjacent to at least one of semiconductor device and in the substrate. At least one of STI region can comprise a nitride layer defining a sidewall surface of the substrate and lining a bottom part of the sidewall surface, an oxide layer lining an upper part of the sidewall surface above the bottom part, and an insulating material in the nitride layer and the oxide layer.

    Abstract translation: 要解决的问题：提供一种能够改善浅沟槽隔离（STI）区域和对应的半导体器件之间的界面特性的电子设备及其制造方法。解决方案：电子设备可以包括衬底，埋置 氧化物（BOX）层，BOX层上的半导体器件中的至少一个以及与半导体器件和衬底中的至少一个相邻的STI区域中的至少一个。 STI区域中的至少一个可以包括限定衬底的侧壁表面并且衬里侧壁表面的底部的氮化物层，衬在底部部分上方的侧壁表面的上部的氧化物层，以及位于衬底的绝缘材料 氮化物层和氧化物层。

    Hybrid coherence protocol
    156.
    发明专利
    Hybrid coherence protocol 有权

    公开(公告)号：JP5265827B2

    公开(公告)日：2013-08-14

    申请号：JP2000301559

    申请日：2000-10-02

    Applicant: エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

    Inventor： シミズ ディー． ,  ジョーンズ アンドリュー

    IPC: G06F12/08

    CPC classification number: G06F12/0835

    Abstract: A computer system having a memory system where at least some of the memory is designated as shared memory. A transaction-based bus mechanism couples to the memory system and includes a cache coherency transaction defined within its transaction set. A processor having a cache memory is coupled to the memory system through the transaction based bus mechanism. A system component coupled to the bus mechanism includes logic for specifying cache coherency policy. Logic within the system component initiates a cache transaction according to the specified cache policy on the bus mechanism. Logic within the processor responds to the initiated cache transaction by executing a cache operation specified by the cache transaction.

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