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    High-speed communication between integrated circuits of an emulation system
    151.
    发明授权
    High-speed communication between integrated circuits of an emulation system 有权

    公开(公告)号：US12099790B1

    公开(公告)日：2024-09-24

    申请号：US17204431

    申请日：2021-03-17

    Applicant: Xilinx, Inc.

    Inventor： Raghukul B. Dikshit ,  Tauheed Ashraf ,  Michael Chyziak

    IPC: G06F30/331 ,  H04J3/06

    CPC classification number: G06F30/331 ,  H04J3/06

    Abstract: An emulation system can include a first integrated circuit (IC) including first circuitry and a first transceiver. The first circuitry is configured to emulate a first partition of a circuit design. The first circuitry is clocked by an emulation clock and the first transceiver is clocked by a transceiver clock asynchronous with the emulation clock. The transceiver clock has a higher frequency than the emulation clock. The emulation system can include a second IC configured to emulate a second partition of the circuit design. The second IC includes a second transceiver. The first transceiver is configured to generate multiplexed emulation data by multiplexing a plurality of nets that cross from the first partition to the second partition of the circuit design. The first transceiver is configured to send the multiplexed emulation data over a serial communication channel to the second transceiver. The multiplexed emulation data includes a clock signal of the first transceiver embedded therein.

    Registration of a PUF signature and regeneration using a trellis decoder
    153.
    发明授权
    Registration of a PUF signature and regeneration using a trellis decoder 有权

    公开(公告)号：US12081238B2

    公开(公告)日：2024-09-03

    申请号：US18084974

    申请日：2022-12-20

    Applicant: Xilinx, Inc.

    Inventor： James Wesselkamper

    IPC: H03M13/25 ,  H03M13/11

    CPC classification number: H03M13/256 ,  H03M13/1111

    Abstract: A physically unclonable function includes a circuit that translates a normally distributed sequence of raw sample into a sequence of uniformly distributed binned values across sub-bins of bins. Helper circuitry generates centering values and parity bits based on binned values generated during registration. Each centering value is associated with a raw sample value corresponding to a binned value and indicates an offset of a sub-bin in one of the bins. A distance calculator generates a set of distances from each raw sample value based on the centering value associated with the raw sample value. Each distance indicates a difference between the respective raw sample value and a raw sample value equivalent to a midpoint of a sub-bin offset by the associated centering value in a bin. A trellis decoder generates a PUF signature based on the candidate symbols, sets of distances, and parity bits.

    DAC-BASED TRANSMIT DRIVER ARCHITECTURE WITH IMPROVED BANDWIDTH
    155.
    发明公开
    DAC-BASED TRANSMIT DRIVER ARCHITECTURE WITH IMPROVED BANDWIDTH 审中-公开

    公开(公告)号：US20240291487A1

    公开(公告)日：2024-08-29

    申请号：US18115588

    申请日：2023-02-28

    Applicant: XILINX, INC.

    Inventor： Li-Yang CHEN ,  Chi Fung POON ,  Chuen-Huei CHOU

    IPC: H03K17/693 ,  H03K17/00

    CPC classification number: H03K17/693 ,  H03K17/005 ,  H04B1/0483 ,  H04B1/40

    Abstract: A transmission system is disclosed including a driver circuit. The driver circuit includes multiplexer circuits that receive parallel data and operate as a differential pair. At least one of the multiplexer circuits is coupled to a first circuit node and a second circuit node of the driver circuit. The at least one the multiplexer circuits outputs serial data from the multiplexer circuits at the first and second circuit nodes. The first and second nodes are coupled to a differential output network. The first and second nodes are coupled to an inductor circuit. The first and second nodes are coupled to a cross-coupled circuit. The inductor circuit drains driver circuit current at the first circuit node. The second circuit node and the cross-coupled circuit steer driver circuit current at the first circuit node and the second circuit node.

    PROTECTING MEMORY CONTROLS AND ADDRESS
    157.
    发明公开
    PROTECTING MEMORY CONTROLS AND ADDRESS 审中-公开

    公开(公告)号：US20240274218A1

    公开(公告)日：2024-08-15

    申请号：US18109744

    申请日：2023-02-14

    Applicant: XILINX, INC.

    Inventor： David TRAN ,  Federico VENINI ,  Sarosh I. AZAD

    IPC: G11C29/52 ,  G11C29/02

    CPC classification number: G11C29/52 ,  G11C29/022

    Abstract: Embodiments herein describe a memory system with a data width (W) that is split into N separate memories each of narrower width W/N. To protect a write enable (WE) signal, the WE signal is toggled and then stored in each of the N memories. For example, toggle circuits can have states that toggle each time the WE signal goes high, indicated that a received data word should be stored in the N memories. A fault on the WE input to any of the N memories results in its stored toggle bit being different from the toggle bits stored in the other N memories. This condition can then be detected upon any subsequent read by checking whether the toggled bits are equal. The memory system can also protect the address and control signals by generating parity bits that are stored in the N memories.

    DOMAIN SPECIFIC MEMORY MANAGEMENT
    158.
    发明公开
    DOMAIN SPECIFIC MEMORY MANAGEMENT 审中-公开

    公开(公告)号：US20240274162A1

    公开(公告)日：2024-08-15

    申请号：US18109229

    申请日：2023-02-13

    Applicant: XILINX, INC.

    Inventor： Jaideep DASTIDAR ,  David James RIDDOCH ,  Steven Leslie POPE

    IPC: G11C7/10 ,  G11C7/24

    CPC classification number: G11C7/1039 ,  G11C7/24

    Abstract: An integrated circuit (IC) device includes functional circuits and multiple communication paths, which may include a first communication path through the functional circuits and a second communication path to permit the functional circuits to share information through a buffer and/or to bypass a subset of the functional circuits and a corresponding portion of the first communication path. The IC device may include a variety of protocol-specific interface circuits (ASIC and/or configurable circuitry) for respective IP blocks, and a controller that selectively directs traffic through the various communication paths. The controller may include a set of domain-specific OpCodes that link various subsets/combinations of the protocol-specific interface circuits as respective communication paths. The IC device may include multiple blocks of circuitry, each including a respective set of domain-specific circuitry (e.g., host-domain, network domain, RF domain, and/or data processing domain), and respective sets of OpCodes.

    ELECTROSTATICS-BASED GLOBAL PLACEMENT OF CIRCUIT DESIGNS HAVING OVERLAPPING REGION CONSTRAINTS
    159.
    发明公开
    ELECTROSTATICS-BASED GLOBAL PLACEMENT OF CIRCUIT DESIGNS HAVING OVERLAPPING REGION CONSTRAINTS 审中-公开

    公开(公告)号：US20240265182A1

    公开(公告)日：2024-08-08

    申请号：US18105605

    申请日：2023-02-03

    Applicant: Xilinx, Inc.

    Inventor： Wuxi Li ,  Mehrdad Eslami Dehkordi

    IPC: G06F30/392 ,  G06F30/398

    CPC classification number: G06F30/392 ,  G06F30/398

    Abstract: Globally placing a circuit design includes adjusting indicated capacity levels for placement bins associated with a target integrated circuit, based on first levels of demand for resources by instances in the circuit design in regions of the target IC. Region constraints restrict placement of the instances in the regions, and the regions include two or more two or more overlapping regions. Tracked levels of demand for resources in the placement bins are adjusted, after adjusting the indicated capacity levels, based on the indicated capacity levels, a target utilization level of the resources in the placement bins, and a current placement. The current placement of the instances is updated based on a density gradient of an electrostatics-based model of the tracked levels of demand, and repeating adjusting the tracked levels of demand and updating the current placement are repeated in response to the density gradient failing to satisfy a threshold.

    DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
    160.
    发明公开
    DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE 审中-公开

    公开(公告)号：US20240264761A1

    公开(公告)日：2024-08-08

    申请号：US18636005

    申请日：2024-04-15

    Applicant: Xilinx, Inc.

    Inventor： Juan J. Noguera Serra

    IPC: G06F3/06 ,  G06F13/16 ,  G06F15/173 ,  G06F15/78

    CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0683 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/7807

    Abstract: A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a memory module of the adjacent DPE and the selected DPE accessing the memory module of a non-adjacent DPE using a DMA circuit and a stream switch of the selected DPE. The subsystem may be in a different die than the DPE array.

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