公开(公告)号：US09984974B1

公开(公告)日：2018-05-29

申请号：US15863986

申请日：2018-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/338 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/06 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.

公开(公告)号：US09899322B2

公开(公告)日：2018-02-20

申请号：US15257921

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/338 ,  H01L23/528 ,  H01L21/768 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

公开(公告)号：US20170330937A1

公开(公告)日：2017-11-16

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/167 ,  H01L29/165 ,  H01L21/265 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/324 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20170301536A1

公开(公告)日：2017-10-19

申请号：US15099581

申请日：2016-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Cheng Yen ,  Tsung-Mu Yang ,  Sheng-Hsu Liu ,  Tsang-Hsuan Wang ,  Chun-Liang Kuo ,  Yu-Ming Hsu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/0262 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02639 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

公开(公告)号：US09754943B1

公开(公告)日：2017-09-05

申请号：US15272425

申请日：2016-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Jiun Chang ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Wei-Hsin Liu ,  Jui-Min Lee ,  Chia-Lung Chang

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L27/10808 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/53295 ,  H01L27/10823 ,  H01L27/10876

Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural word lines and plural bit lines. The word lines are disposed in the substrate along a first trench extending along a first direction. Each of the word lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes TiSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof. The bit lines are disposed over the word lines and extended along a second direction across the first direction.

公开(公告)号：US09691901B2

公开(公告)日：2017-06-27

申请号：US14873214

申请日：2015-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Man-Ling Lu ,  I-Fan Chang ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L21/823814 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.

公开(公告)号：US09530871B1

公开(公告)日：2016-12-27

申请号：US15225836

申请日：2016-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Yueh Tsai ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Jing-Yin Jhang ,  Rung-Yuan Lee ,  Chen-Yi Weng ,  Wei-Jen Wu

IPC: H01L21/8232 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/66795 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的基板; 在鳍状结构上形成外延层; 在外延层上形成第一接触蚀刻停止层（CESL）; 在外延层中形成源/漏区; 并在第一个CESL上形成第二个CESL。

公开(公告)号：US09502305B2

公开(公告)日：2016-11-22

申请号：US14060568

申请日：2013-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。

公开(公告)号：US09443757B1

公开(公告)日：2016-09-13

申请号：US14940120

申请日：2015-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Yueh Tsai ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Jing-Yin Jhang ,  Rung-Yuan Lee ,  Chen-Yi Weng ,  Wei-Jen Wu

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的基板; 在鳍状结构上形成外延层; 在外延层上形成第一接触蚀刻停止层（CESL）; 在外延层中形成源/漏区; 并在第一个CESL上形成第二个CESL。

公开(公告)号：US09397189B2

公开(公告)日：2016-07-19

申请号：US14698828

申请日：2015-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Chien-Chung Huang ,  Chin-Fu Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/263 ,  H01L29/40

CPC classification number: H01L29/4983 ,  H01L21/2633 ,  H01L21/28026 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.