公开(公告)号：US07224234B2

公开(公告)日：2007-05-29

申请号：US11314618

申请日：2005-12-21

Applicant: Ramon A. Gomez

Inventor： Ramon A. Gomez

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03D7/165 ,  H03D7/18 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for-changing PLL operating conditions, in addition to compensating for variable VCO gain.

Abstract translation: 增益补偿器补偿锁相环（PLL）中变容二极管调谐电压调谐振荡器（VCO）的增益变化。 VCO包括具有多个固定电容器的并联LC电路，其可以根据电容器控制信号切换或切换出LC电路，以执行VCO的频带选择调谐。 增益补偿器通过产生基于控制LC电路中的固定电容器的相同电容器控制信号的电荷泵参考电流来补偿可变VCO增益。 增益补偿器通过使用单位电流源复制参考刻度电流来产生电荷泵参考电流。 参考比例电流复制的次数是基于切换到LC电路的固定电容，因此是PLL的频带。 参考比例电流是基于特定于参考频率，环路带宽和环路阻尼等特定PLL特性的PLL控制产生的。 因此，除了补偿可变VCO增益之外，参考泵电流可以有效地优化用于改变PLL工作条件。

公开(公告)号：US07119624B2

公开(公告)日：2006-10-10

申请号：US11096154

申请日：2005-03-30

Applicant: Ramon A. Gomez

Inventor： Ramon A. Gomez

IPC: H03L7/08

CPC classification number: H03L7/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03D7/165 ,  H03D7/18 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

公开(公告)号：US20050174186A1

公开(公告)日：2005-08-11

申请号：US11096154

申请日：2005-03-30

Applicant: Ramon Gomez

Inventor： Ramon Gomez

IPC: H03B1/00 ,  H03B5/12 ,  H03D7/18 ,  H03J5/24 ,  H03L7/00 ,  H03L7/089 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03B5/00

CPC classification number: H03L7/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03D7/165 ,  H03D7/18 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

公开(公告)号：US06882234B2

公开(公告)日：2005-04-19

申请号：US10344154

申请日：2001-08-14

Applicant: Alan C. Young ,  James Harvey ,  Terrence M. P. Percival

Inventor： Alan C. Young ,  James Harvey ,  Terrence M. P. Percival

IPC: H03B5/20 ,  H03B1/00 ,  H03B5/18 ,  H03B21/02 ,  H03C3/40 ,  H03L7/00 ,  H03L7/081 ,  H03L7/099

CPC classification number: H03B5/1841 ,  H03B5/1882 ,  H03B2200/0078 ,  H03B2201/02 ,  H03C3/40 ,  H03L7/081 ,  H03L7/099

Abstract: An oscillator (100, 200) and a method of adjusting the frequency of oscillation of the oscillator (100, 200) are disclosed for generating a signal with an adjustable frequency in a frequency range from 1 GHZ to 200 GHz. The oscillator (100, 200) includes a loop circuit. The loop circuit has an amplifier (101), a delay element or filter (103), a phase shifter (102), a device for adjusting the phase shifter (102), and a coupler (104) to provide an output signal. The adjusting device is coupled to the phase shifter (102).

Abstract translation: 公开了一种振荡器（100,200）和调节振荡器（100,200）的振荡频率的方法，用于在1GHz到200GHz的频率范围内产生具有可调频率的信号。 振荡器（100,200）包括环路电路。 环路电路具有放大器（101），延迟元件或滤波器（103），移相器（102），用于调整移相器（102）的装置和耦合器（104）以提供输出信号。 调节装置耦合到移相器（102）。

公开(公告)号：US6037843A

公开(公告)日：2000-03-14

申请号：US175605

申请日：1998-10-20

Applicant: Kenneth Stephen Hunt

Inventor： Kenneth Stephen Hunt

IPC: H03B1/00 ,  H03B5/12 ,  H03H11/40 ,  H03B5/02 ,  H03H11/48 ,  H03L7/08 ,  H03L7/099

CPC classification number: H03H11/405 ,  H03B5/1206 ,  H03B5/1228 ,  H03B5/1271 ,  H03B2201/02

Abstract: A controllable reactance implemented within an integrated circuit includes a first sub-circuit (20) comprising a reactive element, for example a capacitor 12, coupled in series with a transistor (14). A controllable current source (16) injects a controllable bias current through the transistor (14) to vary the effective resistance of the transistor (14) and hence the effective complex impedance of the capacitor combination. A second transistor (18) amplifies the current to increase the effective capacitance. Preferably, a second sub-circuit (24) includes corresponding components (26, 28, 30) to mirror the real component of the current flowing in the first sub-circuit (20), and transistors (32 and 34) to reflect an inverse current to the coupling node line (22) to cancel the real component of the current at the node, to thus simulate a purely capacitive circuit. An oscillator embodying this circuit is also disclosed. The invention can provide a controllable capacitance without the need for a conventional varactor diode.

Abstract translation: 在集成电路内实现的可控电抗包括第一子电路（20），其包括与晶体管（14）串联耦合的电抗元件（例如电容器12）。 可控电流源（16）通过晶体管（14）注入可控偏置电流，以改变晶体管（14）的有效电阻，从而改变电容器组合的有效复阻抗。 第二晶体管（18）放大电流以增加有效电容。 优选地，第二子电路（24）包括对应于在第一子电路（20）中流动的电流的实分量的对应部件（26,28,30），以及用于反映第一子电路（20）的晶体管（32和34） 电流到耦合节点线（22）以抵消节点处的电流的实部分量，从而模拟纯电容电路。 还公开了体现该电路的振荡器。 本发明可以提供可控电容，而不需要常规的变容二极管。

公开(公告)号：US5872488A

公开(公告)日：1999-02-16

申请号：US749596

申请日：1996-11-15

Applicant: Benny W H Lai

Inventor： Benny W H Lai

IPC: H03K3/282 ,  H03B1/00 ,  H03B5/04 ,  H03C3/09 ,  H03K3/0231 ,  H03K3/03 ,  H03B5/24 ,  H03L1/00 ,  H03L7/099

CPC classification number: H03K3/0231 ,  H03B2201/02

Abstract: A dual input voltage controlled oscillator ("VCO") suitable for use in clock and data recovery ("CDR") systems operating at 100s to 1,000s of MB/sec is described. When a PLL using this VCO is locked onto a data stream of a fixed bit rate, the bang/bang frequency of the VCO does not vary due to process and temperature variation occuring either during manufacture or operation. The VCO is also relatively insensitive to supply voltage variations.

Abstract translation: 描述适用于以100s至1,000s MB / sec工作的时钟和数据恢复（“CDR”）系统的双输入压控振荡器（“VCO”）。 当使用该VCO的PLL被锁定到固定比特率的数据流时，由于在制造或操作期间发生的过程和温度变化，VCO的振荡/振荡频率不变化。 VCO对电源电压变化也相对不敏感。

公开(公告)号：US5614870A

公开(公告)日：1997-03-25

申请号：US530346

申请日：1995-09-28

Applicant: Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

Inventor： Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

IPC: H03B1/00 ,  H03L7/099 ,  H03L7/113 ,  H03L7/14 ,  H04N7/12 ,  H03L7/087

CPC classification number: H04N7/122 ,  H03L7/0991 ,  H03L7/113 ,  H03L7/14 ,  H03B2201/02 ,  H03B2201/0266 ,  H03J2200/10

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract translation: PCT No.PCT / US94 / 04304 Sec。 371 1995年9月28日第 102（e）1995年9月28日PCT PCT 1994年4月19日PCT公布。 公开号WO94 / 26041 日期：1994年11月10日使用锁相环电路的频率检测器来测量振荡器的输出信号的频率和同步信号的频率之间的频率误差。 当同步信号的32个周期中的每个周期中的频率误差超过预定幅度时，锁相环电路以粗频率校正模式开始工作。 只要32个周期没有经过，锁相环电路就工作在空闲的工作模式，并且振荡器不被校正。 结果，在垂直回扫期间，当产生均衡脉冲时，锁相环电路不会受到大的频率误差的干扰。

公开(公告)号：US5610560A

公开(公告)日：1997-03-11

申请号：US525684

申请日：1995-12-11

Applicant: Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

Inventor： Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

IPC: H03B1/00 ,  H03L7/099 ,  H03L7/113 ,  H03L7/14 ,  H04N7/12 ,  H03B5/24

CPC classification number: H04N7/122 ,  H03L7/0991 ,  H03L7/113 ,  H03L7/14 ,  H03B2201/02 ,  H03B2201/0266 ,  H03J2200/10

Abstract: A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.

Abstract translation: PCT No.PCT / US94 / 04404 Sec。 371 1995年12月11日第 102（e）日期1995年12月11日PCT 1994年4月19日PCT PCT。 WO94 / 24767 PCT出版物 日期：1994年10月27日一种锁相环电路包括具有开关电容器的振荡器，其以粗频率误差校正操作模式选择性地耦合到振荡器的正反馈路径。 当频率误差小时，电路在精细的误差校正模式下工作，而不改变切换的无功元件的选择。

公开(公告)号：US5483195A

公开(公告)日：1996-01-09

申请号：US327155

申请日：1994-10-20

Applicant: Anthony K. D. Brown

Inventor： Anthony K. D. Brown

IPC: H03B1/00 ,  H03B5/12 ,  H03B5/20 ,  H03B5/24 ,  H03B27/00 ,  H03F3/45 ,  H03B5/02

CPC classification number: H03B5/20 ,  H03F3/45479 ,  H03B2200/0058 ,  H03B2200/0062 ,  H03B2200/0078 ,  H03B2201/02 ,  H03B27/00 ,  H03B5/24

Abstract: A low noise linear amplifier and a microwave voltage controlled oscillator constructed from such amplifier. Each amplifier within the VCO utilizes a ratioed transistor configuration to generate a linear output over a wide range of inputs. Output current from the amplifier is split into a main output current and components of in-phase and 180.degree. out-of-phase current. A logarithmic tuning control combines the components of in-phase and 180.degree. out-of-phase currents in inverse ratio to provide a constant d.c. feedback current.

Abstract translation: 由这种放大器构成的低噪声线性放大器和微波压控振荡器。 VCO内的每个放大器都使用比例的晶体管配置，以在宽范围的输入端产生线性输出。 放大器的输出电流分为主输出电流和同相和180°异相电流的分量。 对数调谐控制将反相比例的同相和180°异相电流的分量组合在一起，提供恒定的直流电流。 反馈电流。

公开(公告)号：US5298870A

公开(公告)日：1994-03-29

申请号：US908989

申请日：1992-07-06

Applicant: Christopher Cytera ,  Andrew M. Hall

Inventor： Christopher Cytera ,  Andrew M. Hall

IPC: H03B5/12 ,  H03B1/00 ,  H03B5/24 ,  H03B27/00 ,  H03K3/0231 ,  H03L1/00 ,  H03L7/099 ,  H03B5/02

CPC classification number: H03L7/0995 ,  H03B5/24 ,  H03B2200/0038 ,  H03B2200/0058 ,  H03B2200/0062 ,  H03B2200/0078 ,  H03B2201/02 ,  H03B27/00 ,  H03L1/00

Abstract: A voltage controlled oscillator comprises a plurality of differential amplification stages each arranged to introduce a phase shift between its differential input signal and its differential output signal. The frequency at which the desired phase shift occurs can be controlled by adjusting the control signal Vc. The stages are arranged such that the output of one amplifier becomes the input to the next amplifier, making the phase shift additive. Further, a phase shift of 180.degree. may be introduced by inverting the output from one stage before inputting it to the next stage. The total phase shift introduced by the stages is 360.degree.. In this way, an oscillating signal of varying phase shift is produced at the output of each stage. Each stage comprises a standard differential amplifier, well known in the art, having a matched pair of p-channel transistors and a matched pair of n-channel transistors. The differential input is applied to each gate of the n-channel transistor pair, and the differential output is generated at the drains of the n-channel transistor pair.

Abstract translation: 压控振荡器包括多个差分放大级，每个差分放大级被布置为在其差分输入信号与其差分输出信号之间引入相移。 可以通过调节控制信号Vc来控制发生期望相移的频率。 这些级被布置成使得一个放大器的输出变为下一个放大器的输入，使得相移添加剂。 此外，180度的相移可以通过在将其输入到下一级之前将一级的输出反相来引入。 由级引入的总相位为360度。 以这种方式，在每个级的输出处产生变化的相移的振荡信号。 每个级包括本领域公知的具有匹配的一对p沟道晶体管和一对n沟道晶体管的标准差分放大器。 差分输入施加到n沟道晶体管对的每个栅极，并且差分输出在n沟道晶体管对的漏极处产生。