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公开(公告)号：US20200162079A1
公开(公告)日：2020-05-21
申请号：US16661049
申请日：2019-10-23
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost
Abstract: A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.
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公开(公告)号：US10659060B2
公开(公告)日：2020-05-19
申请号：US16143717
申请日：2018-09-27
Applicant: Silicon Laboratories Inc.
Inventor： Timothy A. Monk , Rajesh Thirugnanam
Abstract: A spur cancellation circuit receives a target spur frequency indicative of a frequency of a spur to be canceled and supplies a spur cancellation signal based on the frequency. A frequency tracking circuit tracks a change in the frequency of the spur to be canceled based on a change in phase of the spur cancellation signal and generates an updated target spur frequency based on the change in the frequency of the spur.
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163.发明授权公开(公告)号：US10659045B2
公开(公告)日：2020-05-19
申请号：US15634716
申请日：2017-06-27
Applicant: Silicon Laboratories Inc.
Inventor： Mohamed M. Elsayed
IPC: G01R31/26 , G11C8/08 , H01L21/70 , H03K17/06 , G11C8/00 , H03K19/00 , H03K19/003 , H03K17/16 , H03K19/0185
Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.
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公开(公告)号：US10658999B1
公开(公告)日：2020-05-19
申请号：US16506409
申请日：2019-07-09
Applicant: Silicon Laboratories Inc.
Inventor： Essam S. Atalla , Ruifeng Sun , Mohamed M. Elkholy
Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.
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公开(公告)号：US20200099576A1
公开(公告)日：2020-03-26
申请号：US16137815
申请日：2018-09-21
Applicant: Silicon Laboratories Inc.
Inventor： Christian Salmony Olsen , Jørgen Franck , Peter Shorty , Anders T. Brandt
Abstract: A system and method for improving network resiliency is disclosed. The system includes a network having a plurality of network devices and at least one controller. The controller is configured to create various scenes based on the inputs received from the network devices. The controller is also configured to provide alternate instructions to the network devices in the event that the controller is non-functional. The network devices utilize these alternate instructions when attempts to connect the controller are unsuccessful. In this way, the network is able to operate in a limited way even in the absence of the controller.
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Patent Agency Ranking
166.发明申请公开(公告)号：US20200099337A1
公开(公告)日：2020-03-26
申请号：US16136739
申请日：2018-09-20
Applicant: Silicon Laboratories Inc.
Inventor： Matthew Powell , Sudipta Sarkar
Abstract: Embodiments of clock circuits disclosed herein include a crystal oscillator circuit, an injection oscillator coupled to kick-start the crystal oscillator circuit and a digital frequency calibration circuit coupled to recalibrate the injection oscillator. The crystal oscillator circuit is configured to generate a clock signal at a resonant frequency. The injection oscillator is coupled to supply an oscillation signal at an injection frequency to the crystal oscillator circuit to reduce a start-up time of the crystal oscillator circuit. The digital frequency calibration circuit is coupled to receive the resonant frequency and the injection frequency as inputs, and configured to supply a digital control signal to the injection oscillator to set the injection frequency of the injection oscillator substantially equal to the resonant frequency of the crystal oscillator circuit. Methods are provided herein to recalibrate the injection frequency of an injection oscillator over time, temperature and/or supply voltage.
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公开(公告)号：US10601431B2
公开(公告)日：2020-03-24
申请号：US16022188
申请日：2018-06-28
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Jeffrey L. Sonntag , Brian G. Drost , Volodymyr Kratyuk
Abstract: A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals.
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168.发明授权公开(公告)号：US10587295B1
公开(公告)日：2020-03-10
申请号：US16217494
申请日：2018-12-12
Applicant: SILICON LABORATORIES INC.
Inventor： Terry Lee Dickey , Yan Zhou , Praveen Vangala
Abstract: A wireless receiver including multiple amplifiers coupled in series for amplifying a signal being received, at least one detector that provides a strength indication of the signal being received, multiple AGC schedules each determining a gain reduction schedule for the amplifiers, an AGC schedule selector that selects one of the AGC schedules based on a schedule select input, and an AGC controller that adjusts a gain of at least one of the amplifiers according to a selected AGC schedule based on the strength indication of the signal being received. The AGC schedules may include a first AGC schedule configured for improved SNR performance and a second AGC schedule configured for improved distortion performance. The second AGC schedule may be selected for improved distortion performance when a strong distorting blocker signal is present, and otherwise the first AGC schedule may be selected for better SNR performance.
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公开(公告)号：US20200052814A1
公开(公告)日：2020-02-13
申请号：US16059202
申请日：2018-08-09
Applicant: Silicon Laboratories Inc.
Inventor： Mohammad Sadegh Mohammadi
Abstract: A system and method for determining an optimal configuration of the preamble for use in a wireless network is disclosed. The system and method use the calculated or given channel bit error rate to determine this configuration. There are two important parameters associated with the preamble; its length and the detection threshold. The detection threshold is a measure of how many bits can be incorrect while still detecting the preamble. The optimal value of the detection threshold sets a trade off between false positives and false negatives. In some embodiments, the system uses the channel bit error rate to determine these parameters. In certain embodiments, the detection threshold can be implemented by the receiver without knowledge of the transmitter. By optimizing the configuration of the preamble, the reliability of communications is minimally impacted while power consumption of the network devices is reduced.
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公开(公告)号：US10542585B2
公开(公告)日：2020-01-21
申请号：US15716966
申请日：2017-09-27
Applicant: Silicon Laboratories Inc.
Inventor： DeWitt Clinton Seward , Preston Fick , Clay Daigle , Greg Hodgson , Lee Byrd
Abstract: A system and method for allowing legacy devices to be discovered on a DotDot network is disclosed. The system includes a gateway device to interface between DotDot devices and legacy devices. In some embodiments, the gateway device has a plurality of network interfaces to communicate with these legacy devices. The gateway device discovers the legacy devices that it can communicate with. The gateway device then presents information about these legacy devices in a Resource Directory. In some embodiments, the Resource Directory is maintained within the gateway device. In other embodiments, the gateway device utilizes a Resource Directory that exists on the DotDot network.
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