公开(公告)号：US09029941B2

公开(公告)日：2015-05-12

申请号：US13949968

申请日：2013-07-24

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel ,  Christoph Kadow

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7827

Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.

Abstract translation: 垂直晶体管组件包括具有第一和第二表面的半导体本体，漂移区以及布置在漂移区和第一表面之间的源区和体区。 身体区域也布置在源区域和漂移区域之间。 垂直晶体管部件还包括邻近体区设置的栅极电极，布置在栅极电极和主体区域之间的栅极电介质，以及布置在漂移区域和第二表面之间的漏极区域。 源电极与源区电接触，与栅电极电绝缘并且布置在第一表面上。 漏电极与漏极区域电接触并设置在第二表面上。 栅极接触电极与半导体本体电绝缘，在半导体本体中延伸到第二表面，并与栅电极电连接。

公开(公告)号：US20150091088A1

公开(公告)日：2015-04-02

申请号：US14043971

申请日：2013-10-02

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825

Abstract: An integrated circuit includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Abstract translation: 集成电路包括具有主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，栅电极和与栅电极相邻的栅极电介质。 栅电极设置成与沟道区域的至少两侧相邻。 沟道区域和漂移区域沿着平行于源极区域和漏极区域之间的主表面的第一方向设置。 栅极电介质具有在栅电极的不同位置处变化的厚度。

公开(公告)号：US20140151758A1

公开(公告)日：2014-06-05

申请号：US13692397

申请日：2012-12-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/785

Abstract: A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a ridge extending along the first direction and the drift zone including a superjunction layer stack.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的晶体管。 所述晶体管包括源极区，漏极区，沟道区，漂移区以及与所述沟道区相邻的栅极，所述栅电极被配置为控制在所述沟道区中形成的沟道的导电性。 沟道区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 沟道区具有沿着第一方向延伸的脊的形状，并且漂移区包括超结层层叠。