公开(公告)号：US06511894B2

公开(公告)日：2003-01-28

申请号：US10056009

申请日：2002-01-28

Applicant: Hoon Song

Inventor： Hoon Song

IPC: H01L2130

CPC classification number: B81B7/007 ,  B81B2201/01 ,  H01H59/0009

Abstract: A MEMS relay is provided. The MEMS relay includes a first wafer, a second wafer, and a third wafer that are sequentially stacked. The first wafer includes driving electrodes positioned at the bottom surface of the first wafer, input signal electrodes and output signal electrodes formed adjacent to each other and corresponding to the driving electrodes, via holes formed through the first wafer on the driving electrodes, the input signal electrodes, and the output signal electrodes, and metal pads formed over the via holes. The second wafer includes a body including a sealing unit used to hermetically seal the first and third wafers with the second wafer interposed therebetween, a driving unit which is formed inside and isolated from the body, is an integrated body consisting of a silicon substrate, a passivation layer formed on the silicon substrate, and contact electrodes formed on the passivation layer, and is located lower than the top surface of the body by a predetermined distance, and a connection supporter which extends from two opposing sides of the driving unit to the inner surface of the body. The third wafer includes a hollow in which the driving unit can be rotated.

Abstract translation: 提供了MEMS继电器。 MEMS继电器包括依次层叠的第一晶片，第二晶片和第三晶片。 第一晶片包括位于第一晶片的底表面处的驱动电极，输入信号电极和彼此相邻形成并对应于驱动电极的输出信号电极，通过驱动电极上的第一晶片形成的通孔，输入信号 电极和输出信号电极以及形成在通孔上方的金属焊盘。 第二晶片包括主体，其包括用于密封第一晶片和第三晶片的密封单元，其间插入有第二晶片，形成在主体内部并与主体隔离的驱动单元是由硅基板， 形成在硅衬底上的钝化层和形成在钝化层上的接触电极，并且位于比主体的顶表面低一个预定距离处;以及连接支撑件，其从驱动单元的两个相对侧延伸到内部 身体表面。 第三晶片包括可驱动驱动单元旋转的中空部。

公开(公告)号：KR101800914B1

公开(公告)日：2017-11-23

申请号：KR1020127033926

申请日：2011-06-08

Applicant: 인터내셔널 비지네스 머신즈 코포레이션

Inventor： 던바,조지,에이. ,  허,중-샹 ,  몰링,제프리,씨. ,  머피,윌리암,제이. ,  스탬퍼,앤서니,케이.

IPC: H01L29/84

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: 적어도하나의미세전자기계시스템 (MEMS)를형성하는방법은기판상에하부배선층을형성하는단계를포함한다. 상기방법은상기하부배선층으로부터복수의분리된와이어들 (14)를형성하는단계를더 포함한다. 상기방법은상기복수의분리된와이어들위에전극빔 (38)을형성하는단계를더 포함한다. 상기전극빔과상기복수의분리된와이어들을형성하는단계중 적어도하나는후속실리콘증착 (50)에서힐록(hillock)들과트리플포인트(triple point)들을최소화하는레이아웃으로형성된다.

Abstract translation: 形成至少一个微机电系统（MEMS）的方法包括在衬底上形成下布线层。 该方法还包括从下互连层形成多个分立导线（14）。 该方法进一步包括在多个分立线上形成电极梁（38）。 形成电极梁和多个分立导线的步骤中的至少一个步骤形成为使随后的硅沉积（50）中的小丘和三重点最小化的布局。

公开(公告)号：KR1020130020685A

公开(公告)日：2013-02-27

申请号：KR1020127031138

申请日：2011-06-08

Applicant: 인터내셔널 비지네스 머신즈 코포레이션

Inventor： 헤린,러셀,티. ,  잔스,크리스토퍼,브이. ,  스탬퍼,앤서니,케이. ,  화이트,에릭,제이.

IPC: B81C1/00 ,  B81B3/00 ,  H01H59/00

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: 적어도 하나의 미세전자기계시스템 (MEMS) 캐비티 (60b)를 형성하는 방법은 배선층 (14)와 기판 (10) 위에 제1 희생 캐비티 층 (18)을 형성하는 단계를 포함한다. 상기 방법은 제1 희생 캐비티 층 위에 절연물 층 (40)을 형성하는 단계를 더 포함한다. 상기 방법은 상기 절연물 층에 리버스 다마신 에치백 공정을 수행하는 단계를 더 포함한다. 상기 방법은 상기 절연물 층과 제1 희생 캐비티 층을 평탄화하는 단계를 더 포함한다. 상기 방법은 상기 MEMS의 제1 캐비티 (60b)의 평면의 표면까지 제1 희생 캐비티 층을 벤팅 또는 스트리핑하는 단계를 더 포함한다.

公开(公告)号：KR100991965B1

公开(公告)日：2010-11-04

申请号：KR1020057004845

申请日：2003-09-18

Applicant: 인터내셔널 비지네스 머신즈 코포레이션

Inventor： 친타킨디아닐케이 ,  그로베스로버트에이 ,  스테인케네스제이 ,  수반나세샤드리 ,  볼란트리차드피

IPC: H01G5/16 ,  B81B7/02

CPC classification number: H01G5/18 ,  B81B2201/01 ,  H01G5/011 ,  Y10S257/924

Abstract: 3차원 미세 전자 기계(micro-electromechanical : MEM) 버랙터(varactor)는 가동 전극(50)과 고정 전극(51)이 서로 결합되어 있는 별개의 기판 상에서 제조되는 것으로 개시되었다. 콤-드라이브 전극(comb-drive electrodes)을 갖는 가동 전극은 "칩-사이드(chip side)" 상에 제조되고, 고정된 바닥 전극은 별도의 기판인 "캐리어-사이드(carrier side)" 상에 제조된다. 기판의 양 표면 상에 디바이스를 제조한 후, 칩 사이드 디바이스는 다이싱(diced)되고, "플립-오버(flipped over)"되며, "캐리어" 기판에 대해 정렬되고 접합되어 최종 디바이스를 형성한다. 콤-드라이브(핀(fins)) 전극은 액추에이션(actuation)을 위해 사용되고, 전극의 움직임은 캐패시턴스를 변동시킨다. 포함되어 있는 일정한 구동력에 기인하여, 큰 캐패시턴스 동조 범위(capacitance tuning range)를 획득할 수 있다. 디바이스의 3차원적 측면은 큰 표면 면적을 획득할 수 있게 한다. 큰 종횡비(aspect ratio)를 갖는 형상이 제공되면, 더 낮은 액추에이션 전압을 사용할 수 있다. 제조 시에, MEMS 디바이스는 완전히 인캡슐레이션(encapsulated)되어, 이러한 디바이스에 대한 추가적인 패키지를 필요로 하지 않는다. 또한, 정렬 및 접합은 웨이퍼 스케일(wafer scale)(웨이퍼 스케일 MEMS 패키징(wafer scale MEMS packaging)) 상에서 이뤄질 수 있으므로, 더 저렴한 비용으로 향상된 디바이스 수율을 획득할 수 있다.

公开(公告)号：KR100387239B1

公开(公告)日：2003-06-12

申请号：KR1020010022676

申请日：2001-04-26

Applicant: 삼성전자주식회사

Inventor： 송훈

IPC: H01H59/00

CPC classification number: B81B7/007 ,  B81B2201/01 ,  H01H59/0009

Abstract: A MEMS relay is provided. The MEMS relay includes a first wafer, a second wafer, and a third wafer that are sequentially stacked. The first wafer includes driving electrodes positioned at the bottom surface of the first wafer, input signal electrodes and output signal electrodes formed adjacent to each other and corresponding to the driving electrodes, via holes formed through the first wafer on the driving electrodes, the input signal electrodes, and the output signal electrodes, and metal pads formed over the via holes. The second wafer includes a body including a sealing unit used to hermetically seal the first and third wafers with the second wafer interposed therebetween, a driving unit which is formed inside and isolated from the body, is an integrated body consisting of a silicon substrate, a passivation layer formed on the silicon substrate, and contact electrodes formed on the passivation layer, and is located lower than the top surface of the body by a predetermined distance, and a connection supporter which extends from two opposing sides of the driving unit to the inner surface of the body. The third wafer includes a hollow in which the driving unit can be rotated.

Abstract translation: 提供MEMS继电器。 MEMS中继器包括顺序堆叠的第一晶片，第二晶片和第三晶片。 第一晶片包括位于第一晶片的底表面处的驱动电极，彼此相邻形成并且与驱动电极相对应的输入信号电极和输出信号电极，在驱动电极上通过第一晶片形成的通孔，输入信号 电极和输出信号电极，以及在通孔上形成的金属焊盘。 第二晶片包括：主体，其包括密封单元，该密封单元用于将第一晶片和第三晶片隔着第二晶片气密地密封;驱动单元，其形成在内部并与主体隔离，是由硅衬底， 钝化层，形成在硅基板上;以及接触电极，形成在钝化层上，并且位于比主体的顶面低预定距离的位置处，以及连接支撑件，从驱动单元的两个相对侧延伸到内部 身体的表面。 第三晶片包括驱动单元能够在其中旋转的空洞。

公开(公告)号：US12055927B2

公开(公告)日：2024-08-06

申请号：US17187296

申请日：2021-02-26

Applicant: Honeywell International Inc.

Inventor： Robert Compton ,  Chad Fertig ,  Jeffrey James Kriz

IPC: G05B6/02 ,  B81B3/00 ,  F28F13/00

CPC classification number: G05B6/02 ,  B81B3/0021 ,  F28F13/00 ,  B81B2201/01 ,  B81B2201/018 ,  B81B2203/0181 ,  B81B2203/019 ,  B81B2203/05 ,  B81B2203/058 ,  B81B2207/01 ,  B81B2207/053 ,  F28F2013/008

Abstract: A thermal metamaterial device comprises at least one MEMS thermal switch, including a substrate layer including a first material having a first thermal conductivity, and a thermal bus over a first portion of the substrate layer. The thermal bus includes a second material having a second thermal conductivity higher than the first thermal conductivity. An insulator layer is over a second portion of the substrate layer and includes a third material that is different from the first and second materials. A thermal pad is supported by a first portion of the insulator layer, the thermal pad including the second material and having an overhang portion located over a portion of the thermal bus. When a voltage is applied to the thermal pad, an electrostatic interaction occurs to cause a deflection of the overhang portion toward the thermal bus, thereby providing thermal conductivity between the thermal pad and the thermal bus.

公开(公告)号：US20240199411A1

公开(公告)日：2024-06-20

申请号：US18288063

申请日：2022-04-29

Applicant: Qorvo US, Inc.

Inventor： Robertus Petrus Van Kampen ,  Roberto Gaddi ,  Paul Castillou ,  Lance Barron ,  Julio C. Costa ,  Jonathan Hale Hammond ,  Mickael Renault

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0074 ,  B81B7/007 ,  B81C1/0023 ,  B81C1/00301 ,  B81B2201/01 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/096 ,  B81C2203/0792

Abstract: Various arrangements for a microelectromechanical (MEMS) die and a controller die in vertically stacked structures are disclosed. The orientations of the MEMS die and the controller die vary in the various arrangements. In one embodiment, a backside surface of the MEMS die is operably connected to a frontside surface of the controller die. In another embodiment, a backside surface of the MEMS die is operably connected to a backside surface of the controller die. In another embodiment, a frontside surface of the MEMS die is operably connected to a backside surface of the controller die. In yet another embodiment, a frontside surface of the MEMS die is operably connected to a frontside surface of the controller die.

公开(公告)号：US11854958B2

公开(公告)日：2023-12-26

申请号：US17875205

申请日：2022-07-27

Applicant: General Electric Company

Inventor： Marco Francesco Aimi ,  Joseph Alfred Iannotti ,  Joleyn Eileen Brewer

IPC: H01L21/48 ,  B81C1/00 ,  B81C3/00 ,  H01L21/60 ,  H01L23/522 ,  B81B7/02 ,  B81B7/00 ,  H01L49/02 ,  H01L23/64

CPC classification number: H01L23/5222 ,  B81B7/0074 ,  B81B7/02 ,  B81C1/0015 ,  B81C1/00269 ,  B81C3/001 ,  B81C3/008 ,  H01L21/486 ,  H01L21/4807 ,  H01L28/40 ,  B81B2201/01 ,  H01L23/642 ,  H01L2021/60015

Abstract: A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

公开(公告)号：US20180319652A1

公开(公告)日：2018-11-08

申请号：US16031132

申请日：2018-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Russell T. HERRIN ,  Jeffrey C. MALING ,  Anthony K. STAMPER

IPC: B81B3/00 ,  H01L41/113 ,  B81C1/00

CPC classification number: B81C1/00365 ,  B81B3/0021 ,  B81B3/0072 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

公开(公告)号：US20180174851A1

公开(公告)日：2018-06-21

申请号：US15890465

申请日：2018-02-07

Applicant: THE TRUSTEES OF THE UNIVERSITY OF PENNSYLVANIA

Inventor： Robert W. Carpick ,  Frank Streller ,  Rahul Agarwal ,  Filippo Mangolini

IPC: H01L21/285 ,  C01B33/06 ,  H01L29/45 ,  B81C1/00 ,  B81B3/00 ,  H01L29/84

CPC classification number: H01L21/28518 ,  B81B3/0086 ,  B81B2201/01 ,  B81B2203/04 ,  B81C1/00698 ,  B81C2201/0181 ,  C01B33/06 ,  H01L29/456 ,  H01L29/84

Abstract: The disclosed subject matter provides thin films including a metal silicide and methods for forming such films. The disclosed subject matter can provide techniques for tailoring the electronic structure of metal thin films to produce desirable properties. In example embodiments, the metal silicide can comprise a platinum silicide, such as for example, PtSi, Pt2Si, or Pt3Si. For example, the disclosed subject matter provides methods which include identifying a desired phase of a metal silicide, providing a substrate, depositing at least two film layers on the substrate which include a first layer including amorphous silicon and a second layer including metal contacting the first layer, and annealing the two film layers to form a metal silicide. Methods can be at least one of a source-limited method and a kinetically-limited method. The film layers can be deposited on the substrate using techniques known in the art including, for example, sputter depositing.