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    CRYSTAL OSCILLATOR STARTUP TIME OPTIMIZATION
    171.
    发明申请
    CRYSTAL OSCILLATOR STARTUP TIME OPTIMIZATION 审中-公开

    公开(公告)号：US20200021244A1

    公开(公告)日：2020-01-16

    申请号：US16032348

    申请日：2018-07-11

    Applicant: SILICON LABORATORIES INC.

    Inventor： TIAGO MARQUES ,  CHESTER YU

    IPC: H03B5/06 ,  H03B5/36 ,  H03L3/00

    Abstract: An oscillation circuit including a crystal interface, a crystal amplifier, a level detector, a timing circuit, and a controller. When activated, the crystal amplifier drives a crystal coupled to the crystal interface to establish oscillation, and the level detector indicates when a target amplitude is detected. The controller activates the crystal amplifier and uses the timing circuit and the level detector to measure a startup time of oscillation. The measured startup time is used in calculating a wake up time from a sleep mode in time to perform an operation at a scheduled time. The startup time may be adjusted or averaged and may be remeasured with temperature change. A method of minimizing startup time of a crystal oscillator includes measuring startup time for determining a delay value for programming a wakeup circuit. Robust startup settings may be used in the event of startup failure due to a sleepy crystal.

    Adaptive jitter and spur adjustment for clock circuits
    172.
    发明授权
    Adaptive jitter and spur adjustment for clock circuits 有权

    公开(公告)号：US10511315B1

    公开(公告)日：2019-12-17

    申请号：US16138080

    申请日：2018-09-21

    Applicant: Silicon Laboratories Inc.

    Inventor： Vivek Sarda

    IPC: H03L7/197 ,  H03L7/081 ,  G06F1/08 ,  H03K23/66 ,  H03L7/183

    Abstract: An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.

    Slew-rate controlled supply voltage switching
    174.
    发明授权
    Slew-rate controlled supply voltage switching 有权

    公开(公告)号：US10468983B2

    公开(公告)日：2019-11-05

    申请号：US14933285

    申请日：2015-11-05

    Applicant: SILICON LABORATORIES INC.

    Inventor： Mohamed Mostafa Elsayed ,  Kenneth W. Fernald ,  Matthew Powell

    IPC: H02M3/158 ,  H03K17/04 ,  H02M1/00

    Abstract: An apparatus includes a slew rate regulation circuit, a plurality of switches and a controller circuit. The controller circuit controls the plurality of switches to decouple a first source supply voltage from a supply rail; control the plurality of switches to couple a second source supply voltage to the supply rail to replace the first source supply voltage with the second source supply voltage; and control the slew rate regulation circuit to regulate a slew rate of a voltage of the supply rail during a time interval in which the first source supply voltage is being replaced with the second source supply voltage.

    High output swing high voltage tolerant bus driver
    175.
    发明授权
    High output swing high voltage tolerant bus driver 有权

    公开(公告)号：US10461964B1

    公开(公告)日：2019-10-29

    申请号：US16169757

    申请日：2018-10-24

    Applicant: Silicon Laboratories Inc.

    Inventor： Alexander Cherkassky ,  Bruce P. Del Signore

    IPC: H04L25/02

    Abstract: A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

    NEUTRALIZATION OF PHASE PERTURBATIONS FROM DETERMINISTIC ELECTROMAGNETIC INTERFERENCE
    178.
    发明申请
    NEUTRALIZATION OF PHASE PERTURBATIONS FROM DETERMINISTIC ELECTROMAGNETIC INTERFERENCE 审中-公开

    公开(公告)号：US20190305783A1

    公开(公告)日：2019-10-03

    申请号：US15944567

    申请日：2018-04-03

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Russell Croman ,  Brian G. Drost

    IPC: H03L7/093 ,  H04L7/033 ,  H03L7/087 ,  H03L7/091 ,  H05K1/02

    Abstract: A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.

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