公开(公告)号：US20220318392A1

公开(公告)日：2022-10-06

申请号：US17657027

申请日：2022-03-29

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Franck Albesa ,  Nicolas Anquet

IPC: G06F21/57 ,  G06F21/60 ,  G06F9/4401

Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.

公开(公告)号：US20220198005A1

公开(公告)日：2022-06-23

申请号：US17644711

申请日：2021-12-16

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Diana Moisuc ,  Christophe Eichwald

IPC: G06F21/55 ,  G06F9/30 ,  G06F3/06

Abstract: Method for detecting the linear extraction of information in a processor using an instruction pointer. The method includes monitoring the values of the instruction pointer, determining a number of consecutive increments incrementing the values of the instruction pointer by a constant amount, and generating a detection signal if the number is greater than or equal to a detection threshold.

公开(公告)号：US20220180004A1

公开(公告)日：2022-06-09

申请号：US17544038

申请日：2021-12-07

Applicant: STMICROELECTRONICS SA ,  STMicroelectronics (Alps) SAS

Inventor： Julien Goulier ,  Pascal Bernon

IPC: G06F21/75 ,  H03K3/037 ,  H03K3/84

Abstract: The present description concerns an integrated circuit including, between first and second terminals having a first voltage applied therebetween, a load configured to execute instructions, a circuit for delivering a digital signal having at least two bits from a binary signal and a current output digital-to-analog converter controlled by the digital signal and coupled between the first and second terminals in parallel with the load.

公开(公告)号：US11353905B2

公开(公告)日：2022-06-07

申请号：US16787679

申请日：2020-02-11

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Jean Camiolo ,  Alexandre Pons

IPC: G05F1/575 ,  G01R19/165 ,  G05F3/18 ,  G06F1/26 ,  H03F3/45 ,  H03K3/0233 ,  G05F1/56

Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.

公开(公告)号：US11283353B2

公开(公告)日：2022-03-22

申请号：US16385284

申请日：2019-04-16

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Alps) SAS

Inventor： Francois Druilhe ,  Patrik Arno ,  Alessandro Inglese ,  Michele Alessandro Carrano

IPC: H02M3/158 ,  H02M1/36 ,  H02M1/00

Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.

公开(公告)号：US20220028844A1

公开(公告)日：2022-01-27

申请号：US17374868

申请日：2021-07-13

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Deborah COGONI ,  David AUCHERE ,  Laurent SCHWARTZ ,  Claire Laporte

IPC: H01L25/16 ,  H01G4/38

Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.

公开(公告)号：US20220004217A1

公开(公告)日：2022-01-06

申请号：US17480803

申请日：2021-09-21

Applicant: STMICROELECTRONICS (ALPS) SAS

Inventor： Kuno Lenz

IPC: G05F3/26 ,  G05F1/56

Abstract: In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.

公开(公告)号：US11115061B2

公开(公告)日：2021-09-07

申请号：US17010351

申请日：2020-09-02

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice Romain ,  Mathieu Lisart ,  Patrick Arnould

IPC: H03M13/29 ,  G06F11/10

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

公开(公告)号：US20210240862A1

公开(公告)日：2021-08-05

申请号：US17161194

申请日：2021-01-28

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Gilles PELISSIER ,  Nicolas ANQUET ,  Delphine LE-GOASCOZ

IPC: G06F21/72 ,  H04L9/08 ,  H04L9/32 ,  H04L9/06

Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.

公开(公告)号：US20210234362A1

公开(公告)日：2021-07-29

申请号：US17157555

申请日：2021-01-25

Applicant: STMicroelectronics (Alps) SAS

Inventor： Michel Bouche

IPC: H02H3/20 ,  H02H3/02 ,  H02H3/033

Abstract: An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.