公开(公告)号：JPS6424621A

公开(公告)日：1989-01-26

申请号：JP18173687

申请日：1987-07-21

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H03H17/06 ,  H03H17/02

Abstract: PURPOSE:To attain high speed signal processing with small sized circuit constitu tion by connecting in cascade a 1st FIR type filter (Finite Impulse Response) using a delay line whose basic delay amount is N-sample (N is a natural num ber) and a 2nd FIR filter using a delay line whose basic delay amount is 1 sample with respect to the FIR filter. CONSTITUTION:The 1st FIR filter 1 uses a delay line having basic delay amount of N-sample and consists of L/N-set of N-sample delay devices consisting a delay line of L/N-tap, L/N-set of weighting circuits 22, and an adder 23 having L/N-input. Moreover, the 2nd FIR filter consists of N-piece of one sample delay devices constituting the N-tap of delay line, N-piece of weighting circuits and an adder of N-input. Then the frequency characteristic connecting both filters in cascade is a frequency characteristic repeating the same characteristic for each sample frequency fs, and a steep frequency characteristic as shown in figure (c) is obtained. In such a case, the scale of circuit goes to 1/10. Thus, the titled filter is made suitable for high speed signal processing.

公开(公告)号：JPS63209335A

公开(公告)日：1988-08-30

申请号：JP4132887

申请日：1987-02-26

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H04J1/05

Abstract: PURPOSE:To attain the FDM operation of a fundamental wave filter having a frequency more than a channel frequency interval f by using an interpolation clock m f being m times as much as the f so as to apply sampling and signal processing. CONSTITUTION:Timing sources 4-7 generates a channel clock whose channel frequency interval is f, interpolation clock m f (m is a factor to N) having a frequency being m times as much as f and a multiplexing clock N f being N times as much as f. N-set of samplers 1, -1-1-N receive independent N-set of input signals respectively and apply sampling at the speed of m f. Moreover, the timing sources 4-7 supply the frequency interval f shifted by each N/m sample in the unit of multiplexed clock to m-set of parallel/serial converters 10-1-10-m, and an FDM multiplexing signal of base band is obtained at the output of adders 11, 12. Thus, the FMD operation of the fundamental filter wider than the f is attained.

公开(公告)号：JPS63200635A

公开(公告)日：1988-08-18

申请号：JP3255787

申请日：1987-02-17

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H04J1/05 ,  H04J3/00

Abstract: PURPOSE:To attain a digital transmultiplexer TMUX whose frequency is not limited depending on the frequency interval and flat by receiving an output of N-set of inserted digital subfilters and applying high speed Fourier transformation at the speed of the inserted clock. CONSTITUTION:Delay circuits 12-1-12-N are connected to the output of a time/space division converting switch 11 and N-set of complex base band signals having a coincident timing are generated by applying a delay proportional to the arrival sequence of the corresponding signal. Further, the interpolation digital subfilters 17-1-17-N are connected to the delay circuits 12-1-12-N to apply prescribed filtering based on the timing by the channel clock and the interpolated clock and a filter output is generated at the sampling speed of the interpolated clock. Then the output of the digital subfilters 17-1-17-N is received to apply high speed Fourier transformation at the speed of the interpolated clock. Thus, a flat filter characteristic at each channel band is obtained.

公开(公告)号：JPS63197135A

公开(公告)日：1988-08-16

申请号：JP3056487

申请日：1987-02-10

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H04J13/00 ,  H04B7/216 ,  H04J13/16

Abstract: PURPOSE:To attain optional connection between lots of small-sized earth stations and direct mutual communication by combining frequency multiplex and code division multiplex so as to split a transmission frequency band into lots of channels, thereby assigning the result as an inherent channel to each small size earth station. CONSTITUTION:A small sized inter-earth station communication equipment consists of a transmission section 10 of a small sized earth station, a communication satellite 20 receiving a transmission signal from a reception section 10 and the reception section 30 of an opposite small sized earth station receiving the output of the satellite 20. Then K-kind (K is a natural number) of channel separation numbers of code split multiplex CDM and L-kind (L is a natural number) channels of frequency division multiplex FDM are combined to attain KXN kinds of channel separation numbers and the inherent channel is assigned respectively to each small-sized earth station. Thus, optional connection is attained among lots of small-sized earth stations, a large spread spectrum ratio is given to the transmission section, a large processing gain is obtained at the transmission section and mutual communication is attained directly by using a single frequency band.

公开(公告)号：JPS63194435A

公开(公告)日：1988-08-11

申请号：JP2647487

申请日：1987-02-09

Applicant: NEC CORP ,  KOKUSAI DENSHIN DENWA CO LTD

Inventor： ICHIYOSHI OSAMU ,  TAKAHATA FUMIO

IPC: H04B14/04

Abstract: PURPOSE:To easily realize a desired filter characteristic and to realize a circuit without necessitating adjustment, with high stability, and possible to be miniaturized, by processing all of the data in a digital way without using an analog filter. CONSTITUTION:The titled circuit is operated with a fast clock 104 after reading a timing clock 102 at a D-FF3 by the output of a fast clock generator 2. A fast counter 4 is reset by the start point of the output clock of the FF3, and counts an interpolation time by the clock 104. The output of the counter 4 is latched with a sample timing 103 at a latch circuit 105, and a coefficient corresponding to the interpolation time is outputted from a coefficient ROM6. The output is multiplied by the output of a corresponding shift register 1 at corresponding multipliers 7-1-7-L, and all of the multiplied results are added and outputted by an adder 8. Those outputs are possible to be connected to a communication system in an asynchronous system separated from a digital signal 101. When the signal 101 is the one of one bit, it is enough to prepare one ROM as a FIR type digital filter 9.

公开(公告)号：JPS6374235A

公开(公告)日：1988-04-04

申请号：JP21885486

申请日：1986-09-17

Applicant: NEC CORP

Inventor： YOSHIHARA KATSUSHI ,  ICHIYOSHI OSAMU

IPC: H04J13/00 ,  H04B1/7085

Abstract: PURPOSE:To prevent mis-synchronization of a demodulation section due to correlation between channels by using two waves whose transmission frequencies are apart by a fine frequency DELTAf and corresponding the worst combination of the correlation to each wave. CONSTITUTION:Plural transmission stations sending a data to one receiving station 103 is divided into transmission station groups 101 and 102. Then the transmission station group 101 uses a frequency f1 as an IF of an IF local oscillator 6 and the transmission station group 102 uses a frequency f2 apart from the frequency f12 by the fine frequency DELTAf. The number of channels of this system is 60 and number of combinations where the worst correlation appears is 30 in pairs. Then they are divided into two as 1st and 2nd groups, the transmission station group 101 is assigned to the 1st group, and the transmission station group 102 is assigned to the 2nd group.

公开(公告)号：JPS62245980A

公开(公告)日：1987-10-27

申请号：JP8829786

申请日：1986-04-18

Applicant: NEC CORP ,  NIPPON TELEGRAPH & TELEPHONE

Inventor： ICHIYOSHI OSAMU ,  YOSHIDA NAOMASA ,  KORI TAKEJI ,  KATO SHUZO ,  MORIKURA MASAHIRO

IPC: G01S13/34 ,  G01S7/282 ,  G01S13/28

Abstract: PURPOSE:To save power consumption and to reduce the scale of a circuit by providing an intermediate frequency multiplexer which adds the outputs of the 1st and the 2nd mixers to each other and obtaining a chirp signal of intermediate frequency from the intermediate frequency multiplexer. CONSTITUTION:An address counter 2 accesses addresses of ROMs 3 and 4 with clock pulses obtained from a clock oscillator 1 and parallel bit data read out of the ROMs 3 and 4 are latched by latch circuits 5 and 6 and then converted by D/A converters 7 and 8 from a cosine and a sine digital signal to analog signals respectively. Those two analog signals are used by the mixers 11 and 12 to modulate the output of a carrier oscillator 9 and the output of a pi/2 phase shifter 10 which shifts the output of the oscillator 9; and the modulation outputs are multiplexed by a hybrid 13, thereby obtaining a chirp signal after single side-band modulation on an output side. Thus, the power consumption is reduced and the circuit scale is also reduced.

公开(公告)号：JPS62107559A

公开(公告)日：1987-05-18

申请号：JP24682785

申请日：1985-11-02

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H03D1/22 ,  H03L7/06 ,  H03L7/08 ,  H04L27/22 ,  H04L27/227

Abstract: PURPOSE:To attain sure synchronization locking by providing a frequency discriminating function and applying frequency locking by the frequency discrimination function at asynchronizing state. CONSTITUTION:The output of a cos mixer 3 and the output of a sin mixer 4 pass through the 1st LPF 5 and the 2nd LPF 6 respectively, are fed to the 1st modulator 7 and the 2nd modulator 8, the outputs are synthesized by a synthesizer 9, the output of the synthesizer 9 is fed to a phase comparator 12 and a frequency discriminator 11 and the phase is compared with that of a signal from the 1st pi/2 phase shifter 2. The phase difference between an input intermediate frequency signal 101 and the output signal 102 of a VCO is detected from the output of the phase comparator 12. On the other hand, a signal retarding the input intermediate frequency signal 101 by pi/2 radian by the 2nd pi/2 phase shifter is fed to the frequency discriminator to apply frequency discrimination.

公开(公告)号：JPS61140227A

公开(公告)日：1986-06-27

申请号：JP26253184

申请日：1984-12-12

Applicant: Nec Corp

Inventor： ICHIYOSHI OSAMU

IPC: H04B1/10 ,  H04B7/02

CPC classification number: H04B1/10

Abstract: PURPOSE:To obtain an automatic interference wave canceling circuit excellent in interference wave canceling effect even when there is a time zone in which a desired wave becomes off by supplying a signal generated when the first detecting device detects the absence of the desired wave and the second detecting device detects the presence of the interference wave as the second controlling signal of a sampling holder. CONSTITUTION:When a signal that indicates the absence of the desired wave signal and the presence of all interference waves is generated by a signal off detecting device 14, a signal on detecting devices 15-1-15-n and an AND device 16, it is supplied to sampling holders 22 of error detecting controlling circuits 13-1-13-n as a sample signal SMPL. While the sample signal SMPL of the sample holder 22 is in the state of on, the output of a correlation detector 21 is inputted to a low pass filter as it is, and when the sample signal SMPL becomes the state of off, the output voltage of the sample holder 22 at the moment is maintained at constant in sufficiently long period. Detection of on and off state of the signal is made by the envelope detection of each IF signal and the threshold detection of the detection output.

Abstract translation: 目的：为了获得干扰波消除效果优异的自动干扰波消除电路，即使当通过提供当第一检测装置检测到不需要的波而产生的信号而产生希望波的时间段时，干扰波消除效果也优异，而第二 检测装置检测干扰波的存在作为采样保持器的第二控制信号。 构成：当由信号关闭检测装置14产生指示不存在所需波信号和存在所有干扰波的信号时，检测装置15-1-15-n和AND装置16上的信号 提供给检错控制电路13-1-13-n的采样保持器22作为采样信号SMPL。 当采样架22的采样信号SMPL处于导通状态时，相关检测器21的输出原样输入低通滤波器，当采样信号SMPL成为截止状态时，输出电压 此时的样品保持器22在足够长的时间内保持恒定。 通过每个IF信号的包络检测和检测输出的阈值检测来检测信号的开和关状态。