公开(公告)号：US10750188B2

公开(公告)日：2020-08-18

申请号：US16412106

申请日：2019-05-14

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Mariano Bona ,  Fritz Lebowsky

IPC: H04N19/154 ,  H04N19/132 ,  H04N19/196 ,  H04N19/176 ,  H04N19/895 ,  H04N19/182 ,  H04N19/15 ,  H04N19/103 ,  H04N19/593

Abstract: A method is provided for encoding a digital signal as an encoded signal. The method includes performing a plurality of localized encodings of a digital signal to generate a set of encoded local signals. Localized encodings are performed for a first sample of the digital signal. A plurality of physical quantities is assigned to the first sample. The set of encoded local signals includes an encoded local signal associated with each physical quantity of the plurality of physical quantities. The method further includes analyzing a characteristic associated with an encoded signal to determine a measured value of the characteristic. The encoded signal includes the set of encoded local signals. The method also includes adjusting a first encoding parameter associated with the plurality of localized encodings according to the measured value of the characteristic and a target value of the characteristic. The first encoding parameter is adjusted for a second sample of the digital signal. The second sample is processed after the first sample.

公开(公告)号：US20200257600A1

公开(公告)日：2020-08-13

申请号：US16787508

申请日：2020-02-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean CAMIOLO

IPC: G06F11/22 ,  G06F13/38 ,  G06F1/26 ,  G01R31/50

Abstract: An apparatus is for testing a device to be supplied with power via USB Power Delivery (USB-PD). The apparatus includes at least one USB Type-C connector configured to be connected to the device to be supplied with power to be tested, the at least one USB Type-C connector including a power supply terminal. Processing circuitry of the apparatus is configured to verify that a voltage at the power supply terminal is lower than a first threshold, verify a role of the device, generate requests representative of power supply configurations supported by the role of the device, and verify compatibility of the power supply configurations supported by the device with standardized power supply configurations.

公开(公告)号：US10738985B2

公开(公告)日：2020-08-11

申请号：US16439308

申请日：2019-06-12

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Joseph Hannan ,  Stuart Robertson ,  Romain Coffy ,  Jean-Michel Riviere

IPC: F21V21/00 ,  F21V23/04 ,  F21V23/00 ,  H01L23/00 ,  F21K9/20 ,  H01L33/44 ,  H05B45/00

Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a molded body having an opening permitting the passage of a light beam generated by the light source; one or more surfaces for receiving a diffuser; and first and second conducting pins traversing the molded body.

公开(公告)号：US10728481B2

公开(公告)日：2020-07-28

申请号：US16165586

申请日：2018-10-19

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Nicolas Moeneclaey

IPC: H04N5/3745 ,  H04N5/378 ,  H04N5/357

Abstract: A method is disclosed for operating an imaging device having a matrix of pixels arranged in rows and columns. A polarization voltage is generated on a gate of a main MOS transistor that is connected as diode. The main MOS transistor is coupled between a power supply voltage and a ground circuit. Prior to reading the pixels of a row of the matrix, a plurality of first capacitors are charged with the polarization voltage. The first capacitors are coupled between the gate of the main transistor and a ground node. Upon reading the pixels of the row, the first capacitors are discharged on respective gates of auxiliary transistors coupled between the columns and the ground node so as to switch on the auxiliary transistors and deliver a substantially identical polarization current to each column.

公开(公告)号：US20200227885A1

公开(公告)日：2020-07-16

申请号：US16743856

申请日：2020-01-15

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Denise LEE ,  Neale DUTTON ,  Nicolas MOENECLAEY ,  Jerome ANDRIOT-BALLET

IPC: H01S5/026 ,  H01S5/183 ,  H01S5/042

Abstract: A laser diode driver circuit includes a first pair of contacts and connectors coupled to an anode of the laser diode. An inductance of each of the first pair of contacts and connectors is the same. A second pair of contacts and connectors are coupled to a cathode of the laser diode. An inductance of each of the second pair of contacts and connectors is the same. The laser diode driver circuit also includes current driving circuitry.

公开(公告)号：US20200227382A1

公开(公告)日：2020-07-16

申请号：US16835793

申请日：2020-03-31

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/31

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20200099381A1

公开(公告)日：2020-03-26

申请号：US16560183

申请日：2019-09-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Nicolas Moeneclaey ,  Cedric Tubert ,  Arnaud Authie

IPC: H03L7/091 ,  H03M3/00

Abstract: The invention concerns a device including: first and second detectors of the phase and/or of the frequency of an input signal with respect to first and second reference signals; and a Sigma/Delta converter interpreting outputs of the first or of the second phase and/or frequency detector to determine a propagation time of the input signal.

公开(公告)号：US20200097294A1

公开(公告)日：2020-03-26

申请号：US16573299

申请日：2019-09-17

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Sebastien METZGER ,  Silvia BRINI

IPC: G06F9/38 ,  G06F9/48 ,  G06F12/084 ,  G06F13/16

Abstract: A processor interacts with a memory set including a cache memory, a first memory storing at least a first piece of information in a first information group, and a second memory storing at least a second piece of information in a second information group. In response to a first cache miss and following a first request from the processor for the first piece of information, the first piece of information obtained from the first memory is supplied to the processor. After a second request from the processor for the second piece of information, the second piece of information obtained from the second memory is supplied to the processor, even if the first information group is currently being transferred from the first memory for loading into the cache memory.

公开(公告)号：US10594263B2

公开(公告)日：2020-03-17

申请号：US15983287

申请日：2018-05-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Flavia Amorosa ,  Serge Ramet ,  Daniel Subiela

IPC: H04B1/10 ,  H03F1/02 ,  H03F3/45 ,  H03F3/19 ,  H04L27/14

Abstract: In an embodiment, a differential amplifier includes: an input stage; an output stage coupled to the input stage, the output stage having first and second output terminals; and a feedback circuit coupled to the output stage, where the feedback circuit is configured to dynamically adjust a bias current of the output stage based on voltages of the first and second output terminals.

公开(公告)号：US10578672B2

公开(公告)日：2020-03-03

申请号：US14986053

申请日：2015-12-31

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Jacquet ,  Didier Fuin

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.