公开(公告)号：WO2003021423A3

公开(公告)日：2003-03-13

申请号：PCT/US2002/027970

申请日：2002-09-04

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

IPC: G06F7/48

Abstract: A vector-matrix multiplier unit fully utilizes a 128x128b data path for operand sizes from 8 to 128b and operand types including signed, unsigned or complex, and fixed-, floating-point, polynomial, or Galois-field while maintaining full internal precision. The present disclosure provides a system and method for improving the performance of general-purpose processor, by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multipliers regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

公开(公告)号：WO1997014101A1

公开(公告)日：1997-04-17

申请号：PCT/US1996015914

申请日：1996-10-03

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig, C.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F13/40

CPC classification number: G06F7/768 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/34 ,  G06F13/4013

Abstract: A method and data processing system for transferring data between the system and a memory system using more than one byte ordering convention by incorporating byte order information into instruction codes. The byte order information is coupled to a control unit along with other information characterizing the data transfer operation. In response to the byte order information and the data transfer operation information, the control unit generates a control signal that is coupled to a BPU. The control signal causes the BPU to rearrange the order of bytes in the data being transferred when the byte order information indicates a first byte ordering format. When the byte order information indicates a second byte ordering format, the BPU does not change the order of the bytes in the data being transferred.

Abstract translation: 一种方法和数据处理系统，用于通过将字节顺序信息并入指令代码中，使用多于一个字节排序的方式在系统和存储器系统之间传送数据。 字节顺序信息与表征数据传送操作的其他信息一起耦合到控制单元。 响应于字节顺序信息和数据传送操作信息，控制单元产生耦合到BPU的控制信号。 当字节顺序信息指示第一字节排序格式时，控制信号使BPU重新排列正在传送的数据中的字节顺序。 当字节顺序信息指示第二字节排序格式时，BPU不改变正在传送的数据中的字节顺序。

公开(公告)号：WO1997007450A1

公开(公告)日：1997-02-27

申请号：PCT/US1996013047

申请日：1996-08-16

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig ,  MOUSSOURIS, John

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F07/00

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data throughout of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120). The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

Abstract translation: 一种用于处理和传送媒体数据流的通用可编程媒体处理器（12）。 媒体处理器（12）包括执行单元（100），其在整个媒体数据流中保持基本上峰值数据。 执行单元（100）包括动态分离多精度运算单元（102），可编程开关（104）和可编程扩展数学元件（106）。 高带宽外部接口（124）将基本上峰值速率的媒体数据流提供给通用寄存器文件（110）和执行单元。 存储器管理单元，以及指令和数据高速缓存/缓冲器（118,120）。 通用的可编程媒体处理器（12）被布置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以传输，处理和接收单个或统一的媒体数据流。

公开(公告)号：WO1996037978A1

公开(公告)日：1996-11-28

申请号：PCT/US1996005549

申请日：1996-04-23

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CORRY, Alan, G. ,  MOSTYN, Graham, Y. ,  MICHEL, Jean-Yves

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H04B15/04

CPC classification number: H04B15/04 ,  H04B2215/064

Abstract: The present invention encompasses techniques for reducing digital noise in integrated circuits and circuit assemblies, particularly dense mixed-signal integrated circuits, based upon shaping the noise from the digital circuit and concentrating it in a single, or a small number, of parts of the frequency spectrum. Generally, the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference. As an example, a radio receiver might be designed such that the peaks of the digital noise lie between received channels, outside the band edges of each.

Abstract translation: 本发明包括基于整形来自数字电路的噪声并将其集中在频率的单个或少数部分中的集成电路和电路组件，特别是致密混合信号集成电路中的数字噪声的技术 光谱。 通常，在某些频率下，模拟电路中噪声的存在不太重要，因此可以小心地将来自数字电路的频谱峰值或峰值导致很少或没有干扰。 作为示例，可以设计无线电接收机，使得数字噪声的峰值位于接收的信道之间，每个的频带边缘之外。

公开(公告)号：WO1995022085A1

公开(公告)日：1995-08-17

申请号：PCT/US1995001735

申请日：1995-02-09

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, Jang, Fung ,  MATTHEWS, James, A.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G03F07/20

CPC classification number: G03F1/36 ,  G03F7/70125 ,  G03F7/70433

Abstract: In a lithographical tool utilizing off-axis illumination, masks to provide increased depth of focus and minimize CD differences between certain features are disclosed. A first mask for reducing proximity effects between isolated and densely packed features and increasing depth of focus (DOF) of isolated features is disclosed. The first mask comprises additional lines (214) referred to as scattering bars, disposed next to isolated edges. The bars are spaced a distance from isolated edges such that isolated and densely packed edge gradients substantially match so that proximity effects become negligible. The width of the bars is set so that a maximum DOF range for the isolated feature is achieved. A second mask, that is effective with quadrupole illumination only, is also disclosed. This mask "boosts" intensity levels and consequently DOF ranges for smaller square contacts so that they approximate intensity levels and DOF ranges of larger elongated contacts. Increasing the intensity levels in smaller contacts reduces critical dimension differences between variably sized contact patterns when transferred to a resist layer. The second mask comprises additional openings, referred to as anti-scattering bars, disposed about the square contact openings. The amount of separation between the edge of the smaller contact and the anti-scattering bars determines the amount of increased intensity. The width of the anti-scattering bars determines the amount of increase in DOF range. Both scattering bar and anti-scattering bars are designed to have widths significantly less than the resolution of the exposure tool so that they do not produce a pattern during exposure of photoresist.

Abstract translation: 在利用离轴照明的光刻工具中，公开了提供增加的聚焦深度并最小化某些特征之间的CD差异的掩模。 公开了用于减少隔离和密集堆叠特征之间的邻近效应的第一掩模，并且增加了隔离特征的增加的焦深（DOF）。 第一掩模包括邻近隔离边缘设置的称为散射棒的附加线（214）。 这些杆与隔离边缘间隔开一段距离，使得孤立和密集堆积的边缘梯度基本匹配，使得邻近效应变得可忽略。 条的宽度被设定为使得隔离特征的最大自由度范围达到。 还公开了仅对四极照明有效的第二掩模。 该掩模“增加”强度水平，因此适用于较小的方形触点的DOF范围，使得它们接近较大细长触点的强度水平和DOF范围。 增加较小触点中的强度水平可以减少转移到抗蚀剂层时可变尺寸的接触图案之间的临界尺寸差异。 第二掩模包括围绕正方形接触开口设置的称为防散射棒的附加开口。 较小触点的边缘与抗散射条之间的分离量决定了增加强度的量。 防散射条的宽度决定了DOF范围的增加量。 散射棒和防散射棒都被设计成具有明显小于曝光工具的分辨率的宽度，使得它们在光致抗蚀剂曝光期间不产生图案。

公开(公告)号：WO1994027204A2

公开(公告)日：1994-11-24

申请号：PCT/US1994004614

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  HERNDON, William, H.

IPC: G05F03/24

CPC classification number: G05F3/24

Abstract: The present invention describes a bias potential distribution system which provides bias potentials to MOS devices while ensuring the devices' operating conditions remain constant over temperature, process, and power supply fluctuations. Further, bias potentials are generated at one main location within the logic circuit and then distributed throughout the logic circuit to all of the MOS devices or to bias voltage conversion circuits.

Abstract translation: 本发明描述了一种偏置电位分配系统，其向MOS器件提供偏置电位，同时确保器件的工作条件在温度，过程和电源波动上保持恒定。 此外，在逻辑电路内的一个主要位置处产生偏置电位，然后在整个逻辑电路中分布到所有MOS器件或偏置电压转换电路。

公开(公告)号：WO2003021423A2

公开(公告)日：2003-03-13

申请号：PCT/US2002/027970

申请日：2002-09-04

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

IPC: G06F7/00

CPC classification number: G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/57 ,  G06F7/724 ,  G06F9/30014 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/16 ,  G06F2207/3812 ,  G06F2207/382 ,  G06F2207/3824 ,  G06F2207/3828

Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multipliers regardsless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

Abstract translation: 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 随着操作数大小减小，矩阵和向量操作数的元素数量增加，功能单元完全利用128b乘128b乘法器的全部资源，而不考虑操作数大小。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

公开(公告)号：WO1997014094A1

公开(公告)日：1997-04-17

申请号：PCT/US1996016320

申请日：1996-10-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig, C.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F09/302

CPC classification number: G06F9/30189 ,  G06F9/30014 ,  G06F9/3865

Abstract: A floating-point instruction having incorporated floating point information and a method and system for implementing the floating-point instruction in a computer system is described. The floating point information indicates whether an exception trap should occur and the type of rounding to be performed upon "inexact" arithmetic results. The floating point information further indicates whether other floating-point exception traps should occur. This information allows dynamic (e.g. instruction-by-instruction) modification of various operating parameters of the CPU without modifying information in status registers using special instructions or modes, thereby increasing overall CPU performance. The technique is also supported by several mechanisms for providing precise floating-point exceptions.

Abstract translation: 描述了包含浮点信息的浮点指令以及用于在计算机系统中实现浮点指令的方法和系统。 浮点信息指示是否发生异常陷阱，并在“不精确”运算结果时执行舍入的类型。 浮点信息还指示是否应发生其他浮点异常捕获。 该信息允许在不使用特殊指令或模式修改状态寄存器中的信息的情况下对CPU的各种操作参数进行动态（例如逐个指令）修改，从而提高整体CPU性能。 该技术还通过几种提供精确浮点异常的机制来支持。

公开(公告)号：WO1997007451A2

公开(公告)日：1997-02-27

申请号：PCT/US1996013195

申请日：1996-08-14

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  KARZES, Thomas, J. ,  HANSEN, Craig, C. ,  MASSALIN, Henry

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F07/00

CPC classification number: G06F7/762 ,  G06F7/76 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032

Abstract: A method and system for performing arbitrary permutations of sequences of elements. In the general case, the method of the present invention processes the elements to be permuted as a multi-dimensional array, where each element in the array corresponds to one of the elments to be permuted. The permutation is achieved by performing a sequence of sets of permutations, where each set of permutations in the sequence independently permutes the elements within each one-dimensional slice through the array, along some particular dimension of the array. The total number of sets of permutations, or stages, is one less than twice the number of dimensions in the array. An extension to the general method allows some extensions of permutations which involve the copying of individual elements. A system based on the extended general method implements a large class of operations which involve copying and/or permuting elements, where the sequence of elements is a word of data and the elements are bits of data. An efficient control structure for the system permits control signals to be shared across slices of the array. A version of the system based on a two-dimensional array includes three multiplex stages, where the first stage multiplexes along the rows, the second stage multiplexes along the columns, and the third stage multiplexes across the rows once again. Several classes of computer instructions which generally involve the copying and/or permuting of data are also described.

Abstract translation: 一种用于执行元素序列的任意排列的方法和系统。 在一般情况下，本发明的方法将要置换的元素处理为多维阵列，其中阵列中的每个元素对应于待置换的元素中的一个。 通过执行一组排列来实现置换，其中序列中的每组置换通过阵列沿着阵列的某个特定维度独立地排列每个一维切片内的元素。 排列的集合或阶段的总数量是数组中维度数量的两倍。 一般方法的扩展允许一些涉及复制单个元素的排列扩展。 基于扩展通用方法的系统实现涉及复制和/或置换元素的大类操作，其中元素序列是数据字，元素是数据位。 该系统的有效的控制结构允许控制信号在阵列的切片之间共享。 基于二维阵列的系统的版本包括三个复用级，其中第一级沿着行多路复用，第二级沿着列多路复用，并且第三级再次跨越行多路复用。 还描述了通常涉及数据的复制和/或置换的几类计算机指令。

公开(公告)号：WO1996035145A1

公开(公告)日：1996-11-07

申请号：PCT/US1996005224

申请日：1996-04-17

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  WAMPLER, Kurt, E. ,  LAIDIG, Thomas, L.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G03F07/20

CPC classification number: G03F7/70441 ,  G03F1/36 ,  H01J2237/31762 ,  H01J2237/31769

Abstract: A method for synthesizing correction features for an entire mask pattern that initially divides mask pattern data into tiles of data - each tile representing an overlapping section of the original mask pattern. Each of the tiles of data is sequentially processed through correction feature synthesis phases - each phase synthesizing a different type of correction feature. All of the correction features are synthesized for a given tile before synthesizing the correction features for the next tile. Each correction feature synthesis phase formats the data stored in the tile into a representation that provides information needed to synthesize the correction feature for the given phase. Methods for implementing edge bar and serif correction features synthesis phases are also described. The method for synthesizing external type edge bars is performed by oversizing feature data in the tile by an amount equal to the desired spacing of the external edge bar, formatting the oversized data into an edge representation and expanding each of the edges in the edge representation of the oversized data into edge bars having a predetermined width. Internal type of edge bars for the tile are synthesized by initially inverting feature data and then performing the same steps as for generating the external edge bars. The method for serif synthesis is performed by initially formatting tile data into a vertex representation, eliminating certain of the vertices not requiring serifs, synthesizing a positive serif for each convex corner and a negative vertex for each concave corner, and eliminating any disallowed serifs. Internal bars and negative serifs are "cut-out" of original tile data by performing geometric Boolean operations and external bars and positive serifs are concatenated with the "cut-out" tile data, equivalent to performing a geometric OR operation.

Abstract translation: 一种用于将最初将掩模图案数据划分成数据块的整个掩模图案的校正特征的方法，每个图块表示原始掩模图案的重叠部分。 通过校正特征合成阶段顺序地处理每个数据块，每个相合成不同类型的校正特征。 在为下一个瓦片合成修正特征之前，对于给定的瓦片合成所有校正特征。 每个校正特征合成阶段将存储在瓦片中的数据格式化为提供合成给定阶段的校正特征所需的信息的表示。 还描述了实现边缘条和衬里修正特征合成阶段的方法。 用于合成外部边缘条的方法是通过将瓦片中的特征数据超过等于外部边缘条的期望间隔的量来执行的，将大尺寸数据格式化为边缘表示，并且将边缘表示中的每个边缘扩展 超大数据进入具有预定宽度的边条。 通过初始反转特征数据然后执行与产生外边缘条相同的步骤来合成瓦片的边缘条的内部类型。 用于衬线合成的方法是通过将瓦片数据初始格式化为顶点表示，消除某些不需要衬线的顶点，为每个凸角合成一个正衬线和每个凹角的负顶点，以及消除任何不允许的衬线。 内部柱和负衬里是通过执行几何布尔运算和外部柱而将原始瓦片数据“切出”，正衬线与“切出”瓦片数据连接，相当于执行几何或运算。