公开(公告)号：WO1996021968A1

公开(公告)日：1996-07-18

申请号：PCT/US1995012415

申请日：1995-09-29

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  PETERSON, Kevin, H. ,  MASSALIN, Henry

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H03D03/00

CPC classification number: H03D3/007 ,  H03D2200/005 ,  H03D2200/0052 ,  H03D2200/0062 ,  H03D2200/0072

Abstract: A digital FM demodulator and method for determining phase changes in highly oversampled complex FM digital signals is described. In a first embodiment the FM signal is oversampled with respect to the frequency of its associated modulating signal. In this embodiment a first digital processing stage delays and conjugates the original FM signal. This delayed conjugated original FM signal is then multiplied with the original FM signal to generate a second signal that represents the changes in the phase between samples of the original FM signal. A second processing stage then delays and conjugates the second signal. The delayed conjugated second signal is then multiplied with the original second signal to generate a third signal that represents changes in the phase between samples of the second signal. The imaginary component of the third signal is passed through a digital integrator which outputs the phase changes of the original FM signal. In a second embodiment, the highly oversampled signal is oversampled with respect to the deviation frequency of its associated modulating signal. In this embodiment the center frequency of the original FM signal is frequency shifted to approximately zero frequency. This frequency shifted signal is then delayed and conjugated. The delayed conjugated shifted signal is then multiplied with the original frequency shifted signal; yielding an output signal where the imaginary portion of the output signal is equal to the phase changes of the original FM signal.

Abstract translation: 描述了用于确定高度过采样的复数FM数字信号中的相位变化的数字FM解调器和方法。 在第一实施例中，FM信号相对于其相关调制信号的频率被过采样。 在该实施例中，第一数字处理级延迟并共轭原始FM信号。 然后将该延迟的共轭原始FM信号与原始FM信号相乘以产生表示原始FM信号的样本之间的相位变化的第二信号。 第二处理级然后延迟并共轭第二信号。 然后将延迟的共轭第二信号与原始第二信号相乘以产生表示第二信号的样本之间的相位变化的第三信号。 第三信号的虚分量通过数字积分器，该数字积分器输出原始FM信号的相位变化。 在第二实施例中，高度过采样的信号相对于其相关调制信号的偏差频率被过采样。 在这个实施例中，原始FM信号的中心频率被频移到大致零频率。 然后，该频移信号被延迟并共轭。 然后将延迟的共轭移位信号与原始频移信号相乘; 产生输出信号，其中输出信号的虚部等于原始FM信号的相位变化。

公开(公告)号：WO1996003807A1

公开(公告)日：1996-02-08

申请号：PCT/US1995009349

申请日：1995-07-25

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  MOSTYN, Graham, Y. ,  HERNDON, William, H. ,  MOUSSOURIS, John, P. ,  ROBINSON, Timothy, B. ,  ROSSEEL, Geert, P.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H03K19/0185

CPC classification number: H03K19/0013 ,  H03K19/018507

Abstract: The present invention is an improvement of a digital topology including a logic block portion and a buffer portion. The improved buffer portion of the present invention is implemented with first and second parallel, same conductivity type transmission gates. The transmission gates couple either a first (V1) or second (V2) voltage onto the output of the buffer (55) in response to a logic signal originating from the logic block portion. The first (V1) and second (V2) voltages are selected to be relatively close in magnitude such that the peak-to-peak voltage of the digital output signal seen on the output of the buffer is relatively small. As a result, power consumption for charging the output of the buffer is minimized. In addition, the parallel transmission gates only consume power while charging the output of the buffer so that quiescent power consumption of the buffer is eliminated. Quiescent power dissipation is also eliminated in certain types of logic block designs that include logic gates having constant current sources. This is achieved by enabling the current sources with a pulse signal. The pulse width and magnitude of the pulse signal is selected to allow a latched sense amplifier to sense valid data from the output of the logic block portion during a specified interval. After valid data is sensed, the logic blocks's current sources are disabled, and the logic block portion no longer consumes any power. The sense amplifier is enabled for intervals long enough to capture the data from the logic block and drive the transmission gates with the data. In this configuration, none of the elements in the topology dissipate quiescent power since none of them are constantly operating.

Abstract translation: 本发明是包括逻辑块部分和缓冲部分的数字拓扑的改进。 本发明的改进的缓冲部分由第一和第二平行的相同导电类型的传输门来实现。 响应于源自逻辑块部分的逻辑信号，传输门将第一（V1）或第二（V2）电压耦合到缓冲器（55）的输出上。 第一（V1）和第二（V2）电压被选择为相对接近于幅度，使得在缓冲器的输出端上看到的数字输出信号的峰 - 峰电压相对较小。 结果，对缓冲器的输出进行充电的功耗最小化。 此外，并行传输门仅在缓冲器的输出充电时消耗功率，从而消除了缓冲器的静态功耗。 在包括具有恒定电流源的逻辑门的某些类型的逻辑块设计中也消除了静态功耗。 这是通过使能脉冲信号的电流源实现的。 选择脉冲信号的脉冲宽度和幅度以允许锁存的读出放大器在指定的间隔期间从逻辑块部分的输出检测有效数据。 在检测到有效数据之后，逻辑块的当前源被禁用，并且逻辑块部分不再消耗任何电力。 读出放大器使能间隔足够长的时间来捕获来自逻辑块的数据，并用数据驱动传输门。 在这种配置中，拓扑中的任何元件都不会消耗静态功耗，因为它们都不会持续运行。

公开(公告)号：WO1993014445A1

公开(公告)日：1993-07-22

申请号：PCT/US1993000456

申请日：1993-01-15

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, Jang, Fung ,  MATTHEWS, James, A.

IPC: G03F09/00

CPC classification number: G03F1/36 ,  G03F7/70433 ,  G03F7/70441

Abstract: An improvement for reducing proximity effects comprised of additional lines, referred to as intensity leveling bars, into the mask pattern. The leveling bars perform the function of adjusting the edge intensity gradients of isolated edges in the mask pattern, to match the edge intensity gradients of densely packed edges. Leveling bars are placed parallel to isolated edges such that intensity gradient leveling occurs on all isolated edges of the mask pattern. In addition, the leveling bars are designed to have a width significantly less than the resolution of the exposure tool. Therefore, leveling bars that are present in the mask pattern produce resist patterns that completely developed away when a nominal exposure energy is utilized during exposure of photoresist.

公开(公告)号：WO1997014101A1

公开(公告)日：1997-04-17

申请号：PCT/US1996015914

申请日：1996-10-03

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig, C.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F13/40

CPC classification number: G06F7/768 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/34 ,  G06F13/4013

Abstract: A method and data processing system for transferring data between the system and a memory system using more than one byte ordering convention by incorporating byte order information into instruction codes. The byte order information is coupled to a control unit along with other information characterizing the data transfer operation. In response to the byte order information and the data transfer operation information, the control unit generates a control signal that is coupled to a BPU. The control signal causes the BPU to rearrange the order of bytes in the data being transferred when the byte order information indicates a first byte ordering format. When the byte order information indicates a second byte ordering format, the BPU does not change the order of the bytes in the data being transferred.

Abstract translation: 一种方法和数据处理系统，用于通过将字节顺序信息并入指令代码中，使用多于一个字节排序的方式在系统和存储器系统之间传送数据。 字节顺序信息与表征数据传送操作的其他信息一起耦合到控制单元。 响应于字节顺序信息和数据传送操作信息，控制单元产生耦合到BPU的控制信号。 当字节顺序信息指示第一字节排序格式时，控制信号使BPU重新排列正在传送的数据中的字节顺序。 当字节顺序信息指示第二字节排序格式时，BPU不改变正在传送的数据中的字节顺序。

公开(公告)号：WO1997007450A1

公开(公告)日：1997-02-27

申请号：PCT/US1996013047

申请日：1996-08-16

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig ,  MOUSSOURIS, John

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F07/00

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data throughout of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120). The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

Abstract translation: 一种用于处理和传送媒体数据流的通用可编程媒体处理器（12）。 媒体处理器（12）包括执行单元（100），其在整个媒体数据流中保持基本上峰值数据。 执行单元（100）包括动态分离多精度运算单元（102），可编程开关（104）和可编程扩展数学元件（106）。 高带宽外部接口（124）将基本上峰值速率的媒体数据流提供给通用寄存器文件（110）和执行单元。 存储器管理单元，以及指令和数据高速缓存/缓冲器（118,120）。 通用的可编程媒体处理器（12）被布置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以传输，处理和接收单个或统一的媒体数据流。

公开(公告)号：WO1996037978A1

公开(公告)日：1996-11-28

申请号：PCT/US1996005549

申请日：1996-04-23

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CORRY, Alan, G. ,  MOSTYN, Graham, Y. ,  MICHEL, Jean-Yves

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H04B15/04

CPC classification number: H04B15/04 ,  H04B2215/064

Abstract: The present invention encompasses techniques for reducing digital noise in integrated circuits and circuit assemblies, particularly dense mixed-signal integrated circuits, based upon shaping the noise from the digital circuit and concentrating it in a single, or a small number, of parts of the frequency spectrum. Generally, the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference. As an example, a radio receiver might be designed such that the peaks of the digital noise lie between received channels, outside the band edges of each.

Abstract translation: 本发明包括基于整形来自数字电路的噪声并将其集中在频率的单个或少数部分中的集成电路和电路组件，特别是致密混合信号集成电路中的数字噪声的技术 光谱。 通常，在某些频率下，模拟电路中噪声的存在不太重要，因此可以小心地将来自数字电路的频谱峰值或峰值导致很少或没有干扰。 作为示例，可以设计无线电接收机，使得数字噪声的峰值位于接收的信道之间，每个的频带边缘之外。

公开(公告)号：WO1995022085A1

公开(公告)日：1995-08-17

申请号：PCT/US1995001735

申请日：1995-02-09

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, Jang, Fung ,  MATTHEWS, James, A.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G03F07/20

CPC classification number: G03F1/36 ,  G03F7/70125 ,  G03F7/70433

Abstract: In a lithographical tool utilizing off-axis illumination, masks to provide increased depth of focus and minimize CD differences between certain features are disclosed. A first mask for reducing proximity effects between isolated and densely packed features and increasing depth of focus (DOF) of isolated features is disclosed. The first mask comprises additional lines (214) referred to as scattering bars, disposed next to isolated edges. The bars are spaced a distance from isolated edges such that isolated and densely packed edge gradients substantially match so that proximity effects become negligible. The width of the bars is set so that a maximum DOF range for the isolated feature is achieved. A second mask, that is effective with quadrupole illumination only, is also disclosed. This mask "boosts" intensity levels and consequently DOF ranges for smaller square contacts so that they approximate intensity levels and DOF ranges of larger elongated contacts. Increasing the intensity levels in smaller contacts reduces critical dimension differences between variably sized contact patterns when transferred to a resist layer. The second mask comprises additional openings, referred to as anti-scattering bars, disposed about the square contact openings. The amount of separation between the edge of the smaller contact and the anti-scattering bars determines the amount of increased intensity. The width of the anti-scattering bars determines the amount of increase in DOF range. Both scattering bar and anti-scattering bars are designed to have widths significantly less than the resolution of the exposure tool so that they do not produce a pattern during exposure of photoresist.

Abstract translation: 在利用离轴照明的光刻工具中，公开了提供增加的聚焦深度并最小化某些特征之间的CD差异的掩模。 公开了用于减少隔离和密集堆叠特征之间的邻近效应的第一掩模，并且增加了隔离特征的增加的焦深（DOF）。 第一掩模包括邻近隔离边缘设置的称为散射棒的附加线（214）。 这些杆与隔离边缘间隔开一段距离，使得孤立和密集堆积的边缘梯度基本匹配，使得邻近效应变得可忽略。 条的宽度被设定为使得隔离特征的最大自由度范围达到。 还公开了仅对四极照明有效的第二掩模。 该掩模“增加”强度水平，因此适用于较小的方形触点的DOF范围，使得它们接近较大细长触点的强度水平和DOF范围。 增加较小触点中的强度水平可以减少转移到抗蚀剂层时可变尺寸的接触图案之间的临界尺寸差异。 第二掩模包括围绕正方形接触开口设置的称为防散射棒的附加开口。 较小触点的边缘与抗散射条之间的分离量决定了增加强度的量。 防散射条的宽度决定了DOF范围的增加量。 散射棒和防散射棒都被设计成具有明显小于曝光工具的分辨率的宽度，使得它们在光致抗蚀剂曝光期间不产生图案。

公开(公告)号：WO1994027204A2

公开(公告)日：1994-11-24

申请号：PCT/US1994004614

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  HERNDON, William, H.

IPC: G05F03/24

CPC classification number: G05F3/24

Abstract: The present invention describes a bias potential distribution system which provides bias potentials to MOS devices while ensuring the devices' operating conditions remain constant over temperature, process, and power supply fluctuations. Further, bias potentials are generated at one main location within the logic circuit and then distributed throughout the logic circuit to all of the MOS devices or to bias voltage conversion circuits.

Abstract translation: 本发明描述了一种偏置电位分配系统，其向MOS器件提供偏置电位，同时确保器件的工作条件在温度，过程和电源波动上保持恒定。 此外，在逻辑电路内的一个主要位置处产生偏置电位，然后在整个逻辑电路中分布到所有MOS器件或偏置电压转换电路。

公开(公告)号：WO1998004970A1

公开(公告)日：1998-02-05

申请号：PCT/US1997012651

申请日：1997-07-21

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  LAIDIG, Thomas, L.

IPC: G06F09/00

CPC classification number: G06F17/5081

Abstract: A system for processing geometry which reduces the amount of memory spaces while improving the processing speed. The system delivers vertices in sequence to a vertex queue (70) so that data in the vertex queue is freed as it is delivered and only minimal intermediate results are stored. By this incremental evaluation, less memory space is needed. In another aspect of the invention the vertices are maintained in the proper sequence so that sorting operation can be eliminated. A sorted vertex queue (70) and an unsorted vertex list (72) are utilized so that resorting of the entire vertex list may be prevented. In addition, a compressed format (34) for storing geometry is utilized based on the fact that much information can be rederived from a sorted and reduced vertex queue.

Abstract translation: 一种用于处理几何的系统，其在提高处理速度的同时减少存储空间的量。 系统将顶点顺序传递到顶点队列（70），以便顶点队列中的数据在传递时释放，只存储最小的中间结果。 通过这种增量评估，需要更少的内存空间。 在本发明的另一方面中，顶点以适当的顺序保持，从而可以消除排序操作。 利用排序的顶点队列（70）和未排序的顶点列表（72），从而可以防止整个顶点列表的撤回。 此外，基于可以从排序和缩小的顶点队列重新获取大量信息的事实，利用用于存储几何的压缩格式（34）。

公开(公告)号：WO1996023353A1

公开(公告)日：1996-08-01

申请号：PCT/US1995015219

申请日：1995-11-21

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CORRY, Alan, G.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H03H17/06

CPC classification number: H03H17/0275 ,  H03H17/06

Abstract: A compact FIR filter uses one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing. The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator. The area required to realize an FIR filter for performing real-time filter is therefore reduced.

Abstract translation: 紧凑型FIR滤波器使用紧凑型地址排序器和紧凑型乘法器/累加器中的一个或两者。 地址序列器利用多相FIR滤波器的不同相之间存在的某些对称性，以减少系数存储并简化地址排序。 乘法器/累加器能够在每个时钟周期执行两次乘法/累加操作，避免在某些情况下需要添加第二个乘法器/累加器。 因此，实现用于执行实时滤波器的FIR滤波器所需的面积减少。