Abstract:
PURPOSE: A phase detector of a digital phase locked loop(PLL) is provided, which minimizes a quantization error generated while converting an analog phase difference into digital data, and improves a performance of the digital phase locked loop remarkably. CONSTITUTION: According to the phase detector(310) detecting a phase difference of a frequency in a digital phase locked loop(PLL), a count unit(311) counts numbers repetitively and continuously without reset according to a system clock. A latch unit(312) latches the first count value of the count unit according to an inputted reference clock, and outputs the first count value and the second count value latched at a previous reference clock. And an arithmetic calculation unit calculates a difference between the first count value and the second count value being output from the latch unit. The count unit comprises an N bit counter.
Abstract:
유선 통신망에서의 발신자번호와 콜백모뎀을 이용한 센싱정보 전송장치 및 방법, 그리고 센싱정보 수집장치 및 방법이 개시된다. 본 발명에 따른 센싱정보 전송장치는 적어도 하나의 감지기로부터 센싱정보를 수신하는 감지기 검출부, 감지기 검출부에 의해 수신된 센싱정보를 주기보고 정보와 즉시보고 정보로 분류하는 제어부 및 센싱정보가 주기보고 정보이면 일정한 주기로 센싱정보 수집장치로 발신하여 센싱정보 전송장치에 대응하는 발신자 번호가 센싱정보 수집장치로 전달된 시점에 호를 종료한 후 센싱정보 수집장치로부터의 접속요청 시 모뎀접속을 통해 주기보고 정보를 전송하고, 센싱정보가 즉시보고 정보이면 센싱정보 수집장치로 모뎀접속하여 즉시보고 정보를 전송하는 모뎀부;를 구비한다. 본 발명에 따르면, 유선 통신망을 사용하는 수용가의 통신비 부담을 줄일 수 있고, 다수의 수용가를 최소의 통신회선을 사용하여 동시에 다량으로 발생되는 주기적 또는 비주기적 센싱정보를 디지털 통신 프로토콜 메시지 형태로 오류없이 전송할 수 있다.
Abstract:
Disclosed are an apparatus and a method for managing a memory in a delay tolerant network. The present invention determines a message to be deleted in a memory based on the number of transfers calculated for each message, and deletes the determined message from the memory. According to the present invention, a message to be deleted from a memory is determined and deleted based on the number of transfers calculated for each message so that a message which has not been dispersed much to the network is left in a buffer memory and a message which has been sufficiently dispersed to the network is removed first, making it possible to satisfy basic requirements of management of a memory buffer to increase an overall message transfer rate.
Abstract:
A message transmission device in a delay allowance network considering packet characteristics and a message transmission method are disclosed. A message classification unit classifies messages into predetermined packets according to the predetermined standard. A transmission possibility modification unit calculates a modification transmission possibility value in which a first transmission possibility modification value is modified in order to transmit the message from a transmission node to a destination node. A message transmission unit transmits the message from the transmission node to the reception node when the predetermined condition is satisfied by comparing a second transmission possibility value with the modified transmission possibility value. The present invention can improve a service quality by considering the packet characteristics and transmission possibility defined based on the touch information with the destination node in the PRoPHET protocol of the delay allowance network. [Reference numerals] (110) Message classification unit;(120) Transmission possibility modification unit;(130) Message transmission unit
Abstract:
PURPOSE: A TU signal pointer processing apparatus and a method therefor are provided to reduce the capacity of a logical circuit by performing a time-division processing and installing a state storing unit and reduce a unit cost by manufacturing the logical circuit as an ASIC. CONSTITUTION: A clock generator(660) generates write, read, process clocks, and address and system clocks for storing and reading position information and valid information among received AU-3 signals. A reception state storing unit(670) stores a current reception state of every sequential logical circuit of a receiving signal pointer processor(630) for every time slot of an AU-3 signal received on the basis of read, process and write timing that have been generated by the clock generator. A transmission state storing unit(680) stores a current transmission state of every sequential logical circuit of a transmission signal pointer processor(650) for every time slot of a received AU-3 signal. The receiving signal pointer processor(530) performs a pointer process function, generates position information of V5 byte, and stores the current reception state of the sequential logical circuit in the reception state storing unit(670). An elastic buffer(640) temporarily stores valid information among the AU-3 signals and stores the position information. The transmission signal pointer processor(650) generates a point signal value to be outputted, multiplexes it with a valid information signal to generate a re-aligned AU-3 signal, and stores the current transmission state of the sequential logical circuit in the transmission state storing unit(680).
Abstract:
지연 허용 네트워크에서의 메모리 관리 장치 및 방법이 개시된다. 본 발명은, 메시지별로 계산된 메시지 통합 전달 횟수를 기초로 메모리에서 삭제할 메시지를 결정하고, 결정된 메시지를 메모리에서 삭제한다. 본 발명에 따르면, 메시지별로 계산된 메시지 통합 전달 횟수를 기초로 메모리에서 삭제할 메시지를 결정하여 삭제함으로써, 네트워크에 아직 많이 확산되지 않은 메시지는 버퍼 메모리에 남겨 두고 네트워크에 이미 충분히 확산된 메시지를 우선적으로 제거하여 전체적인 메시지 전달율을 높이고자 하는 메모리 버퍼 관리의 기본 요구사항을 더 우수하게 충족시킬 수 있다.