公开(公告)号：WO2008001189A3

公开(公告)日：2008-03-27

申请号：PCT/IB2007001733

申请日：2007-06-26

Applicant: AXALTO SA ,  WILIANTO WILIANTO ,  SJARIF KRISHNA

Inventor： WILIANTO WILIANTO ,  SJARIF KRISHNA

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/484

Abstract: The invention relates to a personal token running a series of applications (A, B, C, D, E), characterized in that it comprises a thread controller (TC) which transmits data from the applications (A, B, C, D, E) to an external device (TS) in a cyclic way, a cycle being constituted of a series of data transfers (1A, 2A, 3A ) from the applications (A, B, C, D, E) and to the external device (TS), a cycle comprising a respective number of data transfers dedicated to each respective application (A, B, C, D, E) which is different according to the respective application (A, B, C, D, E), the number of data transfers for a respective application (A, B, C, D, E) in a cycle corresponding to a priority level of the application (A, B, C, D, E) as taken into account by the thread controller (TC).

Abstract translation: 本发明涉及一种运行一系列应用（A，B，C，D，E）的个人令牌，其特征在于它包括一个线程控制器（TC），它从应用程序（A，B，C，D， E）以循环的方式连接到外部设备（TS），该循环由来自应用程序（A，B，C，D，E）的一系列数据传输（1A，2A，3A）和外部设备 （A），（B），（C），（D），（E）中，每个相应应用程序（A，B，C，D，E）专用的相应数量的数据传送的循环， （A，B，C，D，E）的相应应用程序（A，B，C，D，E）的优先级相对应的周期中的数据传输的数量 TC）。

公开(公告)号：WO2007132331A8

公开(公告)日：2008-03-20

申请号：PCT/IB2007001237

申请日：2007-05-11

Applicant: AXALTO SA ,  JOFFRAY OLIVIER

Inventor： JOFFRAY OLIVIER

IPC: H04M1/73 ,  G06K19/07

CPC classification number: G06K19/07 ,  G06F12/0246 ,  G06F2212/1028 ,  G06K19/0701 ,  H04M1/72519 ,  H04M2250/14 ,  H04W52/0261 ,  Y02D10/13 ,  Y02D70/00 ,  Y02D70/1222

Abstract: To reduce the power consumption of the chip card of a mobile telephone according to the power supply status of the said telephone, the electrically erasable memory is managed according to the power supply status of the mobile device. Are thus proposed a memory management process for a removable object placed in a mobile device, a mobile device and a chip card. The removable object includes at least a primary non-volatile memory and a secondary non-volatile memory. The secondary memory is electrically erasable in blocks. The removable object is informed by the mobile device of the power supply status of the mobile device. According to the power supply status of the mobile device, the erasing of the secondary memory is always authorised (31), partially authorised (35, 36) or forbidden (34).

Abstract translation: 为了根据所述电话的电源状态降低移动电话的芯片卡的功耗，根据移动设备的电源状态来管理电可擦除存储器。 因此提出了用于放置在移动设备，移动设备和芯片卡中的可移动对象的存储器管理过程。 可拆卸对象至少包括主非易失性存储器和辅助非易失性存储器。 二次存储器可以块状电可擦除。 可移动物体由移动设备通知移动设备的电源状态。 根据移动设备的电源状态，二级存储器的擦除总是被授权（31），部分授权（35,36）或禁止（34）。

公开(公告)号：WO2007144737A3

公开(公告)日：2008-02-28

申请号：PCT/IB2007001556

申请日：2007-06-08

Applicant: AXALTO SA ,  GANEM HERVE

Inventor： GANEM HERVE

IPC: G06F21/34 ,  G06F21/43 ,  G07F7/10 ,  H04L29/06 ,  H04L29/08

CPC classification number: H04L29/06027 ,  G06F21/34 ,  G06F21/43 ,  G06Q20/341 ,  G07F7/10 ,  H04L63/0853 ,  H04L63/18 ,  H04L65/1006 ,  H04L65/1069 ,  H04L67/14

Abstract: The invention relates to a personal token (10) comprising a microprocessor and a memory, said personal token (10) storing and running a software entity which constitutes an end-point for communication over the internet, characterized in that the software entity constitutes an end-point according to a signaling protocol over the internet which signaling protocol is of the type intended at initiating a session (20, 30, 40, 50, 60) of real-time conferencing between end-points.

Abstract translation: 本发明涉及包含微处理器和存储器的个人令牌（10），所述个人令牌（10）存储并运行构成通过因特网进行通信的端点的软件实体，其特征在于，软件实体构成一个终端 根据互联网上的信令协议，信令协议是用于发起端点之间的实时会议的会话（20,30,40,50,60）的类型。

公开(公告)号：WO2007096735A3

公开(公告)日：2007-12-06

申请号：PCT/IB2007000392

申请日：2007-02-15

Applicant: AXALTO SA ,  SARAN SWAMI ,  BHARGAV YUGANT

Inventor： SARAN SWAMI ,  BHARGAV YUGANT

IPC: H04L29/06

CPC classification number: H04L63/0853 ,  H04L63/14 ,  H04W12/06 ,  H04W12/12

Abstract: The invention relates to an authentication token (10) for a communication network comprising a microprocessor (11), a memory (12), a stored secret key (Ki) and a set of instructions for controlling the microprocessor (11) into performing an authentication calculation on the basis of a received random (RAND) and on the basis of the stored secret key, characterized in that it includes a memory location dedicated for storing a counter value and it includes instructions for making the counter value evolve each time the authentication calculation is performed.

Abstract translation: 本发明涉及一种用于通信网络的认证令牌（10），其包括微处理器（11），存储器（12），存储的秘密密钥（Ki）和用于控制微处理器（11）执行认证的一组指令 基于所接收的随机（RAND）并且基于所存储的秘密密钥进行计算，其特征在于，其包括专用于存储计数器值的存储器位置，并且其包括用于在每次认证计算时使计数器值发展的指令 被执行。

公开(公告)号：WO2007132331A1

公开(公告)日：2007-11-22

申请号：PCT/IB2007/001237

申请日：2007-05-11

Applicant: AXALTO SA ,  JOFFRAY, Olivier

Inventor： JOFFRAY, Olivier

IPC: H04M1/73 ,  G06K19/07

CPC classification number: G06K19/07 ,  G06F12/0246 ,  G06F2212/1028 ,  G06K19/0701 ,  H04M1/72519 ,  H04M2250/14 ,  H04W52/0261 ,  Y02D10/13 ,  Y02D70/1222

Abstract: To reduce the power consumption of the chip card of a mobile telephone according to the power supply status of the said telephone, the electrically erasable memory is managed according to the power supply status of the mobile device. Are thus proposed a memory management process for a removable object placed in a mobile device, a mobile device and a chip card. The removable object includes at least a primary non-volatile memory and a secondary non-volatile memory. The secondary memory is electrically erasable in blocks. The removable object is informed by the mobile device of the power supply status of the mobile device. According to the power supply status of the mobile device, the erasing of the secondary memory is always authorised (31), partially authorised (35, 36) or forbidden (34).

Abstract translation: 为了根据所述电话的电源状态降低移动电话的芯片卡的功耗，根据移动设备的电源状态来管理电可擦除存储器。 因此提出了用于放置在移动设备，移动设备和芯片卡中的可移动对象的存储器管理过程。 可拆卸对象至少包括主非易失性存储器和辅助非易失性存储器。 二次存储器可以块状电可擦除。 可移动物体由移动设备通知移动设备的电源状态。 根据移动设备的电源状态，二级存储器的擦除总是被授权（31），部分授权（35,36）或禁止（34）。

公开(公告)号：WO2007116262A1

公开(公告)日：2007-10-18

申请号：PCT/IB2007/000728

申请日：2007-03-23

Applicant: AXALTO SA ,  VIGILANT, David ,  FUMAROLI, Guillaume

Inventor： VIGILANT, David ,  FUMAROLI, Guillaume

IPC: G06F7/72

CPC classification number: G06F7/723 ,  G06F2207/7238 ,  H04L9/003 ,  H04L2209/04

Abstract: The invention relates to a cryptographic mechanism and to a cryptographic device incorporating such cryptographic mechanism. The cryptographic mechanism offers a better resistance to side channel attacks than that of known cryptographic mechanisms by incorporating a new type of masking mechanism.

Abstract translation: 本发明涉及一种加密机制以及包含这种密码机制的密码装置。 通过结合一种新型的掩蔽机制，加密机制提供了比已知密码机制更好的抵抗侧面信道攻击的能力。

公开(公告)号：WO2007107868A3

公开(公告)日：2007-09-27

申请号：PCT/IB2007/000729

申请日：2007-03-22

Applicant: AXALTO SA ,  LU, HongQuian Karen

Inventor： LU, HongQuian Karen

IPC: H04L29/06 ,  G06F21/20

Abstract: The invention relates to a system comprising a network device (NSC), a host computer (HOST) and a remote server (SRV). The host computer (HOST) and the network device (NSC) are connectable through a network. The host computer (HOST) and the remote server (SRV) are connectable through the Internet. The network device (NSC) comprises a web server accessible from the host computer (HOST). The network device (NSC) is set to store a user's authentication credential. The host computer (HOST) is set to display a web page produced by the remote server (SRV) to the user. The remote server (SRV) is set to include a login link in said web page, the login link pointing to said web server. The web server is set to display a login page to the user on the host computer (HOST) when the user clicks on said login link, in order to authenticate the user. Upon authentication of the user, the network device (NSC) is set to send the user's authentication credential to the remote server (SRV) in order to authenticate the user to the remote server (SRV).

公开(公告)号：WO2007072202A1

公开(公告)日：2007-06-28

申请号：PCT/IB2006/003741

申请日：2006-12-19

Applicant: AXALTO SA ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ,  BRUN, Jean ,  BALERAS, François ,  PORNIN, Jean-Louis ,  MATHIEU, Lydie ,  BONVALOT-DUBOIS, Béatrice ,  ROUMEGOUX, Julien ,  DEPOUTOT, Frédéric

Inventor： BRUN, Jean ,  BALERAS, François ,  PORNIN, Jean-Louis ,  MATHIEU, Lydie ,  BONVALOT-DUBOIS, Béatrice ,  ROUMEGOUX, Julien ,  DEPOUTOT, Frédéric

IPC: H01L23/485

CPC classification number: H01L24/10 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49855 ,  H01L23/573 ,  H01L24/13 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16105 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81899 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The microcomponent (1) has a first wafer (2), equipped with multiple electrical connection pins (5), a second wafer (7), equipped with multiple electrical connection pads (8), intended to cooperate with the electrical connection pins (5) of the first wafer (2). The second wafer (7) has multiple first interconnection pins (10), formed on the electrical connection pads (8) of the second wafer (7), positioned facing the electrical connection pins (5) of the first wafer (2) and coming into contact with each other by nesting. An interconnection process for the first (2) and second (7) wafers of the microcomponent (1) consisting of at least the stages of the formation of the pins (5) of the first wafer (2), for example by electro-chemical growth, and of the formation of the pins (10) of the second wafer (7), for example by chemical growth.

Abstract translation: 微组件（1）具有配备有多个电连接销（5）的第一晶片（2），配备有多个电连接焊盘（8）的第二晶片（7），其旨在与电连接销（5）配合 ）的第一晶片（2）。 第二晶片（7）具有形成在第二晶片（7）的电连接焊盘（8）上的多个第一互连引脚（10），其面向第一晶片（2）的电连接引脚（5）定位并且到来 通过嵌套相互接触。 用于微组件（1）的第一（2）和第二（7）晶片的互连工艺包括至少形成第一晶片（2）的引脚（5）的阶段，例如通过电化学 生长和第二晶片（7）的引脚（10）的形成，例如通过化学生长。

公开(公告)号：WO2007054802A2

公开(公告)日：2007-05-18

申请号：PCT/IB2006003173

申请日：2006-11-10

Applicant: AXALTO SA ,  SION JEROME

Inventor： SION JEROME

CPC classification number: H04L63/10 ,  G06F17/3089 ,  H04L67/14

Abstract: The invention relates to a subscriber identity module (1) comprising at least one integrated circuit, said subscriber identity module (1) comprising a web server module (11) accessible by or through a terminal (2) via a first data transfer protocol (P1), characterized in that said subscriber identity module (1) further comprises a storage device (12) for storing data generated by means of said terminal (2) and a blog management module (10) defining an interface for selecting among the data stored in the storage device (12) selected data which are accessible by or through said terminal (2) via the first data transfer protocol (P1).

Abstract translation: 本发明涉及一种包括至少一个集成电路的用户识别模块（1），所述用户识别模块（1）包括经由终端（2）经由第一数据传输协议（P1 ），其特征在于，所述用户识别模块（1）还包括用于存储通过所述终端（2）生成的数据的存储设备（12）和定义用于在存储的数据中选择的数据的界面的博客管理模块（10） 所述存储设备（12）经由所述第一数据传输协议（P1）可由或经所述终端（2）访问的所选数据。

公开(公告)号：WO2007042928A2

公开(公告)日：2007-04-19

申请号：PCT/IB2006002860

申请日：2006-10-06

Applicant: AXALTO SA ,  ST MICROELECTRONICS SA ,  LEYDIER ROBERT ,  POMET ALAIN ,  DUVAL BENJAMIN

Inventor： LEYDIER ROBERT ,  POMET ALAIN ,  DUVAL BENJAMIN

IPC: G06F1/04 ,  H03L7/197

CPC classification number: G06F1/04 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156 ,  H03K2005/00058 ,  H04L7/0338

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal f(0) to f(2 i -1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal f(0) to j(2 i -1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal f(0) to f(2 i -1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract translation: 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号f（0）至f（2-i-1）被提供有基本的时间步长。 在接收到的比特流内测量与比特持续时间相对应的时间步长的合理数量。 振荡器信号f（0）至j（2≤I-1）被变换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号f（0）至f （2 i），两个连续的有效边缘被分离成与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。