公开(公告)号：EP1173885A4

公开(公告)日：2009-05-27

申请号：EP00922179

申请日：2000-04-13

Applicant: CBL TECHNOLOGIES INC ,  PANASONIC CORP

Inventor： SOLOMON GLENN S ,  MILLER DAVID J ,  UEDA TETSUZO

IPC: C30B29/38 ,  H01L21/205 ,  H01L33/00 ,  H01L21/31

CPC classification number: H01L21/0262 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/0254 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12576

Abstract: A method for forming an epitaxial layer (4) involves depositing a buffer layer (2) on a substrate (1) by a first deposition process, followed by deposition of an epitaxial layer (4) by a second deposition process. By using such a dual process, the first and second deposition processes can be optimized, with respect to performance, growth rate, and cost, for different materials of each layer. A semiconductor heterostructure prepared by a dual deposition process includes a buffer layer (2) formed on a substrate by MOCVD, and an epitaxial layer (4) formed on the buffer layer (2), the eptitaxial layer deposited by hydride vapor-phase deposition.

公开(公告)号：EP1185727A1

公开(公告)日：2002-03-13

申请号：EP00925996.1

申请日：2000-04-13

Applicant: CBL Technologies, Inc. ,  MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： SOLOMON, Glenn, S. ,  MILLER, David, J. ,  UEDA, Tetsuzo

IPC: C30B23/06 ,  C30B25/10 ,  C30B25/14 ,  C30B29/38 ,  C30B29/40

CPC classification number: C30B25/10 ,  C23C16/4405 ,  C30B29/40 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262

Abstract: A method for forming a relatively thick epitaxial film of a III-V compound on a non-native substrate (40) involves sequentially forming a plurality of epitaxial layers on the substrate at a growth temperature (41). By cooling the substrate and each sequentially grown epitaxial layer to a sub-growth temperature (42) prior to resumption of epitaxial growth, (45, 46) stress within the sample is periodically relieved. Sequential epitaxial growth is combined with system etching (44) to provide an epitaxial layer which not only has a lower propensity to shatter, but also exhibits improved surface morphology. Sequential hydride vapor-phase epitaxy using HCl as both source gas and etchant, allows integration of sequential deposition and system etching into a single process (47, 48).

公开(公告)号：EP1185727A4

公开(公告)日：2006-11-29

申请号：EP00925996

申请日：2000-04-13

Applicant: CBL TECHNOLOGIES INC ,  MATSUSHITA ELECTRIC IND CO LTD

Inventor： SOLOMON GLENN S ,  MILLER DAVID J ,  UEDA TETSUZO

IPC: C30B25/10 ,  C30B29/38 ,  C23C16/34 ,  C30B25/02 ,  C30B25/14 ,  C30B29/40 ,  H01L21/20 ,  H01L21/205 ,  H01L33/00

CPC classification number: C30B25/10 ,  C23C16/4405 ,  C30B29/40 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262

Abstract: A method for forming a relatively thick epitaxial film of a III-V compound on a non-native substrate (40) involves sequentially forming a plurality of epitaxial layers on the substrate at a growth temperature (41). By cooling the substrate and each sequentially grown epitaxial layer to a sub-growth temperature (42) prior to resumption of epitaxial growth, (45, 46) stress within the sample is periodically relieved. Sequential epitaxial growth is combined with system etching (44) to provide an epitaxial layer which not only has a lower propensity to shatter, but also exhibits improved surface morphology. Sequential hydride vapor-phase epitaxy using HCl as both source gas and etchant, allows integration of sequential deposition and system etching into a single process (47, 48).

公开(公告)号：EP1173885A1

公开(公告)日：2002-01-23

申请号：EP00922179.7

申请日：2000-04-13

Applicant: CBL Technologies, Inc. ,  MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： SOLOMON, Glenn, S. ,  MILLER, David, J. ,  UEDA, Tetsuzo

IPC: H01L21/31

CPC classification number: H01L21/0262 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/0254 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12576

Abstract: A method for forming an epitaxial layer (4) involves depositing a buffer layer (2) on a substrate (1) by a first deposition process, followed by deposition of an epitaxial layer (4) by a second deposition process. By using such a dual process, the first and second deposition processes can be optimized, with respect to performance, growth rate, and cost, for different materials of each layer. A semiconductor heterostructure prepared by a dual deposition process includes a buffer layer (2) formed on a substrate by MOCVD, and an epitaxial layer (4) formed on the buffer layer (2), the eptitaxial layer deposited by hydride vapor-phase deposition.